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9.5 Retention Time Optimization for eDRAM in 22nm Tri

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Retention Time Optimization for eDRAM in 22nm Tri-Gate CMOS Technology
Yih Wang, Umut Arslan, Nabhendra Bisnik, Ruth Brain, Swaroop Ghosh, Fatih Hamzaoglu, Nick Lindert,
Mesut Meterelliyoz, Joodong Park, Shigeki Tomishima and Kevin Zhang
Logic Technology Development, Intel Corporation, Hillsboro, Oregon, U.S.A. Email:[email protected]
Abstract
A high performance eDRAM technology has been
developed on a high-performance and low-power 22nm
tri-gate CMOS SoC technology.
By applying noise
reduction circuit techniques and extensive device and
design co-optimization on eDRAM bitcell and critical
circuits, over 100μs retention time at 95°C has been
achieved for a Gbit eDRAM with robust manufacturing
yield.
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