Amba AXI to APB bridge

Amba AXI to APB bridge
ΔΟΥΛΗΣ ΜΙΧΑΗΛ
ΗΛΙΟΥΔΗ ΑΦΡΟΔΙΤΗ
ΜΠΕΛΛΟΣ ΔΗΜΗΤΡΙΟΣ
CE330 - Σχεδίαση Συστημάτων VLSI
Overview
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About Bridge - Simple configuration.
AXI interface
APB bus
Circuit Block Diagram
Circuit Functionality, Read Transfer
Circuit Functionality, Write Transfer
DC set up file
DC script file
About AXI to APB bridge
● The component can be used to connect between AXI
and APB domains.
● Component features:
○ 32-bit AXI slave and APB master interfaces
○ Supports up to 6 connected APB peripherals
○ Supports single active transfer only
Simple Configuration
Amba AXI Interface 1/3
● high-performance
● high-frequency system designs
● suitable for a high-speed submicron interconnect
○ separate address/control and data phases
○ support for unaligned data transfers using byte strobes
○ separate read and write data channels
○ ability to issue multiple outstanding addresses
○ out-of-order transaction completion
○ burst-based transactions with only start address issued
Amba AXI Interface 2/3
● Channel Handshake Process
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The source generates the VALID signal to indicate when the data or
control information is available.
The destination generates the READY signal to indicate that it accepts
the data or control information.
Transfer occurs only when both the VALID and READY signals are
HIGH.
■ Write address channel
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■
■
■
Write data channel
Write response channel
Read address channel
Read data channel
NOTE: The relationship between the address, read, write, and write response
channels is flexible.
Amba AXI Interface 3/3
● Addressing Options
○
The AXI protocol is burst-based.
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Burst length - AWLEN or ARLEN
Burst size - ARSIZE or AWSIZE
● AXI Data Buses
○ The AXI protocol has two independent data buses, one
for read data and one for write data. Data buses have
their own individual handshake signals.
■
data transfers occur on both buses at the same time.
Amba APB bus 1/3
● low-cost
● optimized for minimal power consumption
● reduced interface complexity
○ The APB has unpipelined protocol.
○ All signal transitions are only related to the rising
edge of the clock.
○ Every transfer takes at least two cycles.
Amba APB bus 2/3
APB BUS SIGNALS:
PADDR [APB bridge] - The APB address bus. It can be up to 32 bits wide.
PSELx [APB bridge] - It indicates that the slave device is selected and that a
data transfer is required.
PENABLE [APB bridge] - Indicates the second and subsequent cycles of an
APB transfer.
PWRITE [APB bridge] - Indicates an APB write access when HIGH and an APB
read access when LOW.
PWDATA [APB bridge] - Write data. Up to 32 bits wide.
PREADY [Slave interface] - The slave uses this signal to extend an APB
transfer.
PRDATA [Slave interface] - Read Data. Up to 32-bits wide.
PSLVERR [Slave interface] - This signal indicates a transfer failure.
Amba APB bus 3/3
IDLE:
the default state of the bus
SETUP:
When a transfer
is required the bus moves
into this state. It only
remains in the SETUP state
for one clock cycle.
ACCESS:
The address, write, select, and
write data signals must remain stable
during the transition from the SETUP
to ACCESS state. Exit from the ACCESS
state is controlled by the PREADY signal
from the slave.
Circuit Block Diagram
Circuit Functionality, Read
Transfer 1/4
○
Η αίτηση για το transfer σηματοδοτείται από τα ARADDR και
ARVALID.
■ If ARVALID == 1 πρόκειται για read transaction.
○
To CMD περνάει τις εισόδους και το read σε δικά του wires και από
εκεί στην FIFO.
■ Αν έχει τελειώσει το προηγούμενο transfer κάνει pop τα νέα
στοιχεία για το current transfer που στην περίπτωσή μας είναι
read.
■ Tα signals αποστέλονται στο MUX για την επιλογή του ανάλογου
slave.
○
To MUX επιλέγει το slave αναθέτοντας το αντίστοιχο psel.
■ Καθορίζονται οι είσοδοι pready, pslverr, prdata_pre.
■ If (pready & psel) ==1 τότε περνάει τα data σε wire.
Circuit Functionality,
Read Transfer 2/4
○
Στo CTRL
■ If WVALID ==1, pwrite = WVALID(φαίνεται στην ανάθεση του
wstart και στο ανάλογο always-block) .Επομένως στην
προκειμένη περίπτωση pwrite = 0.
■ Καθορίζονται τα penable, psel, busy & pwrite.
○
Το RD αν "έχει" την άδεια του CTRL πραγματοποιεί το transfer με τα
σήματα-outputs RID, RDATA, RRESP, RLAST, RVALID.
○
Τέλος ελέγχει τις τιμές των outputs και δίνει τιμή στο finish_rd και το
busy, ώστε το CMD να συνεχίσει για το επόμενο transfer.
Circuit Functionality,
Read Transfer 3/4
● CMD
○ INPUTS:
ARADDR,ARID,ARVALID,ALEN,ASIZE,AREADY,AERR,
finish_rd.
○ OUTPUTS:
cmd_id,cmd_addr,cmd_err,cmd_read,cmd_empty,
cmd_full.
● MUX
○ INPUTS:
psel,cmd_addr,pready(i),pslv_err(i),prdata(i).
○ OUTPUTS:
pready,pslv_err,prdata,psel(i).
Circuit Functionality,
Read Transfer 4/4
● CTRL
○ INPUTS:
finish_rd,WVALID,cmd_empty,cmd_read,pready
○ OUTPUTS:
psel,penable,pwrite
● RD
○ INPUTS:
psel,penable,pwrite,prdata,pslverr,pready,cmd_err,
RREADY
○ OUTPUTS:
RID,RDATA,RRESP,RLAST,RVALID,finish_rd
Read transfer flow
Circuit Functionality,
Write Transfer
● Το write transfer γίνεται με παρόμοιο τρόπο
(παραπλήσια ονόματα signals) εκτος από τις εξής
αλλαγές :
○ To MUX παίρνει όλες τις εισόδους εκτός από το
prdata.
○ To WR περνάει τα signals στο output του master.
○ Τέλος στο top level component γίνεται ανάθεση της
εισόδου WDATA στο output pwdata.
DC Setup File
set search_path ". /synopsys/libraries/syn
$search_path"
set target_library "saed90nm_min_pg.db"
set synthetic_library "standard.sldb
dw_foundation.sldb"
set link_library "* $target_library
$synthetic_library"
set symbol_library "saed90nm_min_pg.db"
define_design_lib MY_WORK -path ./WORK
Script File 1/3
● Analyze
analyze
analyze
analyze
analyze
analyze
analyze
analyze
-format
-format
-format
-format
-format
-format
-format
verilog
verilog
verilog
verilog
verilog
verilog
verilog
● Elaborate
elaborate axi2apb
./axi2apb.v
./axi2apb_cmd.v
./axi2apb_ctrl.v
./axi2apb_mux.v
./axi2apb_rd.v
./axi2apb_wr.v
./prgen_fifo.v
Script File 2/3
● Optimization constraints
(exceptions/structural/area/clock)
set_max_delay .5 -to [all_outputs]
set_max_fanout 8
max_area 100
create_clock clk -period 1.800
● Constraint Validation
check_design
Script File 3/3
ungroup -flatten -all
set_flatten true -effort high
uniquify
compile
● Outline
report_area
report_timing
write -f verilog axi2apb -output axi2apb_post_synth.v hierarchy

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