November 2008 Hands-on Workshop: How to Use Ultra-Low Cost RS08 Processors in Real-Time Applications PZ113 Kenny Ji Systems and Applications Engineering TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Curta Calculator в–єCurta вЂў a small, hand-cranked mechanical calculator introduced in 1948 в–єFeatures вЂў Addition вЂў Subtraction вЂў Multiplication вЂў Division вЂў Square roots в–єAdvantages вЂў Easy to use вЂў Portable вЂў No battery needed! вЂў ... Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Core вЂ“ Curta in Silicon в–єRS08 Core вЂў Optimized Memory Organization High code density for 16-KB Memory size Вѓ High efficient access to first 256 bytes Вѓ вЂў Optimized instruction set Compact instruction set for high code density Вѓ Simplified HCS08 Instruction set for code porting Вѓ вЂў Simplified stacking and calling mechanism вЂў Polling Interrupt Mechanism Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Target Applications Вѕ Target Applications Вѕ Ultra-bright LED Application вЂ“ MR16 Bulb Вѕ Low End Thermal Controlled BLDC Fan вЂ“ KA2 Replacing Analog Driver Вѕ Low End Remote Control in Light Dimmer, Light Switch, Electric Fan -- KA2 Replacing ASIC / 4-bit MCU Вѕ Toaster Oven Application вЂ“ KA2 Replacing ASIC Вѕ AC Voltage Line Monitor Вѕ Low End Microwave Oven Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM First EETimes China ACE (Awards for Creativity in Electronics) Best Product of the Year in Microcontrollers (MCUs) Category - MC9RS08KA family вЂўFinalist in EE Times America ACE Award Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Objective and Agenda в–єObjectives: Address field concerns on the RS08 MCU in Real-time applications. вЂў Provide RS08 Real-time solutions. вЂў в–єAgenda: RS08 Architecture вЂў Interrupt Mechanism used in RS08 CPU вЂў Вѓ Вѓ вЂў Real-time solutions for RS08 MCU Вѓ Вѓ вЂў Nested Interrupt VS non-Nested Interrupt Event Based scheduling High efficient scheduling Examples FAQ Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Small but Powerful RS08 Architecture TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. RS08 Core CPU Model в–є CPU вЂў Central Processing Unit вЂў Processing most algorithm & logic operations в–є BDC вЂў Background Debug Controller вЂў Providing background debug capability for RS08 CPU в–є MMC вЂў Memory Mapping Controller вЂў Providing memory accessing capability in RS08 core в–є IMU вЂў Integration Management Unit вЂў Interfacing RS08 core to external logic Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. CPU CPU BDC BDC MMC MMC IMU IMU BUS TM RS08 Core CPU Model в–єCPU Registers вЂў A вЂ“ Accumulator вЂў PC вЂ“ Program Counter вЂў SPC вЂ“ Shadow Program Counter вЂў CCR вЂ“ Condition Code Register в–єMemory Mapped Registers вЂў D[X] вЂ“ Indexed Data Register @0x000E вЂў X вЂ“ Index Register @0x000F вЂў PAGESEL вЂ“ Page Select Register @0x001F Accumulator (A) Program Counter (PC) Shadow Program Counter (SPC) Condition Code Register (CCR) ZZ CC Indexed Data Register (D[X]) Index Register (X) Page Select Register (PAGESEL) Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Memory Map and Addressing Mode в–єMemory Map вЂў Direct Page Fast Access RAM Вѓ Paging Window Short Addressing High Page Registers Nonvolatile Memory Direct Addressing Вѓ вЂў вЂў Fast Access RAM Tiny Addressing D[X] X Frequently Used Registers PAGESEL RAM Unimplemented в–єAddressing Mode вЂў Inherent Addressing Mode (INH) вЂў Relative Addressing Mode (REL) вЂў Immediate Addressing Mode (IMM) вЂў Tiny Addressing Mode (TNY) вЂў Short Addressing Mode (SRT) вЂў Direct Addressing Mode (DIR) вЂў Extended Addressing Mode (EXT) вЂў Indexed Addressing Mode Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Paging Window Unimplemented High Page Registers Unimplemented Nonvolatile Memory TM Optimized Instruction Set в–єOptimized Instructions вЂў вЂў Most Opcode are encoded in Tiny and Short Addressing Modes Tiny and Short Addressing Modes saving at least 1 bytes per instruction which maximizes code density and is quite suitable for small applications = Tiny Addressing = Short Addressing Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Stacking and Calling в–єStacking вЂў No hardware stack management to simplify stacking maintain вЂў No special registers needed for stack operations вЂў Software stack management as alternate method if necessary в–єCalling вЂў Shadow Program Counter (SPC) вЂў Register-based instead of RAMbased calling stack operation for quick calling вЂў SHA and SLA instruction used for more than nested calling Accumulator (A) SHA instruction SLA instruction Program Counter (PC) return from calling Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Jump to calling Shadow Program Counter (SPC) TM Polling Mode Interrupt Schedule RS08 Interrupt Mechanism TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. RS08 Interrupts Model в–єRS08 Application Model вЂў The time based event model allows software sorts interrupt priorities and selects the top one to execute. вЂў Time based event model does not use interrupt vector table as it will prevent the interrupt priorities sort. вЂў Time based event model can maximize the usage of code and minimize RAM size. Executing ISR Executing ISR ISR Return from ISR Interrupted Interrupted Return from ISR Background Background Background Running Wait/Stop Go to Wait or Stop ISR Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Background Time Direction TM How does RS08 CPU service interrupts в–єPolling mode interrupt CPU will be waked up from wait and stop modes when an interrupt occurs. вЂў The corresponding interrupt bit in system interrupt pending register (SIP) will be set. вЂў The program flow is scheduled by polling SIP register. вЂў ISR priority is software defined. вЂў в–єTarget Applications State machine вЂў Time based event applications вЂў Event base applications вЂў Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Traditional Interrupts Operation в–є в–є в–є в–є в–є /* This column shows a typical background program for a interrupt-based schedule */ в–є /* background program */ в–є в–є в–є void main(void) { /* do any initialization here */ ng ri te En R IS в–є в–є в–є в–є в–є /* enter the background, loop forever */ while(1) { /* do lowest priority tasks here*/ ... } } /* interrupt service routine */ в–є в–є в–є interrupt void ISR1(void) { /* do interrupt triggered tasks в–є here */ в–є ... в–є} R IS /* enable interrupts */ в–є ng ti ci Ex в–є в–є в–є в–є /* This column shows a typical interrupt service loop program в–є for a interrupt-based schedule */ в–є в–є в–є interrupt void ISR2(void) { As main program can be interrupted at any anywhere unmasked, a /*time doand interrupt triggered lot of stacking tasks here */operation is made to save в–є ...the status, which will take much time and many memories. в–є} Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Interrupts Operation /* This column shows an RS08 background program for a interrupt-based schedule */ в–є в–є в–є /* This column shows a typical interrupt service loop program for a interrupt-based schedule */ в–є /* background program */ в–є /* interrupt service routine */ в–є в–є в–є в–є в–є в–є void main(void) { ... while(1) { stop(); // stop until arise в–є в–є в–є void ISR1(void) { /* do interrupt triggered tasks here */ ... } R IS в–є в–є ng ti ci Ex if (interrupt 1 triggered) { ISR1(); continue; } if (interrupt 2 triggered) { ISR2(); continue; } ... в–є в–є в–є в–є в–є void ISR2(void) { /* do interrupt triggered tasks here */ ... } RS08 polling mode controls the program stream wholly so that no stacking operation is needed and minimal latency is required. R IS в–є в–є в–є в–є в–є в–є в–є в–є в–є в–є в–є в–є в–є ng ri te En в–є в–є в–є } } Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Benefits of RS08 Interrupt Mechanism в–єMore вЂў available code space As no vector table needed, RS08 core can utilize 32 bytes reserved for HC08 vector table. в–єMinimized вЂў As no stacking operation, RS08 core need no hardware stack and no big memory support. в–єMinimized вЂў interrupt latency As no stacking operation, RS08 core need few cycles to enter and exit from interrupt service routine (ISR). в–єIncreased вЂў вЂў RAM size performance 10-MHz BUS Reduced cycle count for RAM access Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Target Real-time Applications A Timing-base RS08 schedule example TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Timing Base RS08 Core Schedule в–єTiming Based RS08 Core Schedule вЂў The main idea is intended to split big tasks into small fragment so that it can be schedule in a timing slot. вЂў The timing is handled by hardware timer. вЂў As far as the ISR is small enough, the total time period can be occupied by a scheduled task. вЂў All tasks pended are prioritized so that the pended task will always be serviced firstly Timing Period = T T T T Time Direction Task A Task B Background Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. ISR + Scheduler TM Timing Base RS08 Core Schedule Set Hardware Timing Source 1. вЂў вЂў Select a hardware timer as timing source Keep Timing ISR as short as possible Tasks Allocation 2. вЂў вЂў Split big task into small fragment Prioritize Tasks Schedule Tasks after timing ISR 3. вЂў вЂў Schedule task when timing ISR is completed Schedule the pended task with top priority to execute Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Set Hardware Timing Source в–єSelect a hardware timer as timing source вЂў Hardware timer has more accuracy than software вЂў Hardware timer is standard peripheral of MCU в–єKeep Timing ISR as short as possible вЂў Timing is only a source to execute split tasks вЂў Keep ISR short means more time for task execution MTIM: 8-bit Modulo RTI: Fixed Modulo, 1, 2, 4, 8, ..., 1024 CLK CLK INT INT FLAG FLAG TPM: 16-bit Modulo Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Task Allocation в–єSplit big task into small fragment вЂў Most tasks are big and difficult to handle вЂў Make sure each split task can completed execution within a timing period в–єPrioritize Tasks вЂў Only one task can be executed in one timing period вЂў The scheduler need input to arbiter the right task to execute while more than one tasks are pended High Priority AA BB EE FF CC GG 3 Tasks: 2 big and 1 small EE FF AA BB GG 6 Tasks: All small Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Low Priority CC 6 prioritized Tasks: 3 Level Green: high Priority Yellow: middle Priority Blue: Low Priority TM Schedule Tasks after timing ISR в–єSchedule task when timing ISR вЂў ISR is the trigger of every schedule is completed в–єSchedule the pended task with high priority to execute вЂў The pended task with high priority must be service prior to the one with low priority вЂў The tasks with same priority will be scheduled by time order вЂў No task is scheduled if there is no pended task High Priority EE FF AA BB EE FF AA BB CC GG CC GG Low Priority Time Direction Background Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. ISR + Scheduler TM An Example of Timing-Based Schedule в–єPreliminary Requirements вЂў To get RMS value of utility power вЂў 64 times sampling each cycle вЂў Report Final result to host via UART 110V 60Hz/220V 50Hz RS08 CPU 10 ms Trigger/Sample Timer CPU ADC To host ADC Sample 50Hz/60Hz Г— 128 SCI PMC Internal Clock 10-MHz BUS Vaverage = 63 в€‘V i =0 2 i Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM An Example of Timing-Based Schedule в–єBasic Analysis 60 x 64 = 3840 times ADC samplings per second вЂў 60 x 64 = 3840 times square and accumulation operations per second вЂў One square root operation per second вЂў One UART operation вЂў в–єSystem Design 7680Hz (130.2us) Timing вЂў Start ADC every two timings in timing ISR вЂў Get ADC value and perform square and accumulation operations in the next period to the one starting ADC вЂў For the periods not performing square operation are allocated to perform square root operation and UART operation вЂў Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM An Example of Timing-Based Schedule Timing Period = 130.2us T = 130.2us T = 130.2us T = 130.2us Time Direction Task to perform square root and send data via UART Background Task to perform square and accumulation operations ISR staring ADC sampling ISR not staring ADC sampling Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Performance Вѕ Performance Вѕ BUS Frequency: 8-MHz Вѕ Base time period: 130us Вѕ Scheduler code (Flash): 57 bytes Вѕ Scheduler data (RAM): 4 bytes Вѕ ISR code (Flash): 16 bytes Вѕ ISR data (RAM): 1 byte Вѕ Scheduler + ISR execution time: 9us* Вѕ Scheduler + ISR execution time: 12.5us Вѕ Scheduler + ISR CPU load: 9.6% Вѕ Conclusion Вѕ Over 90% MIPS are used for calculation Вѕ RS08 core did a real-time schedule successfully Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Conclusions & FAQ Select best MCU for your applications TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. Select Best MCU for Your Applications в–єWhat best MCU? вЂў Meeting requirements Вѓ Вѓ Вѓ вЂў Never over requirements Never under requirements Exact meeting always Cost acceptable Never being asked why it costs so much Вѓ Minimized development and manufacture cost Вѓ вЂў Least development cycle time Вѓ вЂў Always speeding your prototype to markets The best MCU always most suitable to Applications Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM What applications does RS08 target в–єApplications Small code density < 12K Bytes вЂў RAM < 256 Bytes вЂў No nested interrupt requirement вЂў A small or empty background loop вЂў в–єScheduling State machine вЂў Time based event applications вЂў Event base applications вЂў Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM FAQ в–єQ : Why do we need RS08 core when polling mode looks to be able to be implemented in a traditional CPU? в–єA : RS08 core can wake CPU from stop mode but release the program stream handle to software. A traditional CPU can not use polling mode as they can not be waken up from stop without interrupt vector support. And, if vector table is not used, why do you spend money on it? в–єQ : Does RS08 core have any limitations? в–єA : Of course. RS08 has a strong capability to deal with less tasks (<=6) program. But the polling mode will not always work when the task becomes more. Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Related Session Resources Session Location вЂ“ Online Literature Library http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=052577903644CB Sessions Session ID Title Demos Pedestal ID Demo Title Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM BACKUP S08 VS RS08 Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Advantages в–єReduced Code Size Every S08 vector occupies 2 bytes to store address. S08 uses a fixed interrupt vector table, 32 Г— 2 = 64 bytes. At least 6 bytes are needed to stack current registers when an interrupt occurs. вЂў Every RS08 polling occupies 3 bytes to store opcode. RS08 supports up to 16 interrupts, which means up to 16 Г— 3 = 48 bytes will be used. No stacking operation is needed in RS08 interrupt mechanism. вЂў в–єConclusion вЂў RS08 uses LESS space than traditional interrupt vector. Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Advantages Size for Interrupt Vector S08 VS RS08 Size performance 80 60 64 64 64 64 64 64 15 18 40 20 0 3 0 6 9 1 2 12 3 4 5 64 48 16 Interrupt Number Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Advantages в–єTime Performance S08 takes at least 11 cycles before entering ISR and at least 9 cycles after ISR. S08 takes 20 cycles at least to process ISR associated action. вЂў RS08 takes 5 cycles before entering ISR and 3 cycles after ISR. RS08 takes 5 Г— Priority + 8 cycles to process ISR associated action. вЂў в–єConclusion вЂў For RS08 uses a software scheduling interrupt vector, Вѓ Вѓ Priority #0, Priority #1, and #2 ISR executions are FASTER than S08 ISR. Priority #3 or higher ISR executions is SLOWER than S08 ISR. Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM RS08 Advantage S08 VS RS08 Interrupt Latency BUS cycles 40 30 20 10 20 8 20 13 0 1 20 18 23 20 2 3 33 28 20 20 0 4 5 Number of Interrupt Sources Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Use Cases в–єConsider two cases Case 1: High priority interrupt with high frequency, Low priority interrupt with low frequency. Assuming high priority interrupt has double frequency of adjacent low priority interrupt. вЂў Case 2: Low priority interrupt with high frequency, High priority interrupt with low frequency. Assuming high priority interrupt has half frequency of adjacent low priority interrupt in Case 2. The maximum frequency is 10kHz. вЂў в–єOther assumption Assuming there are up to 6 major interrupts used. Assuming the maximum frequency is 10kHz. Assuming there are no redundancy in background program except the scheduler. вЂў Assuming 10-MHz BUS used for schedule consumption calculation вЂў вЂў вЂў Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Use Cases RS08 Case 1 RS08 Case 2 S08 Freq Cycle Sum Freq Cycle Sum Freq Cycle Sum Priority #0 10000 8 80000 312.5 8 2500 10000 20 200000 Priority #1 5000 13 65000 625 13 8125 5000 20 100000 Priority #2 2500 21 45000 1250 21 22500 2500 20 50000 Priority #3 1250 26 28750 2500 26 57500 1250 20 25000 Priority #4 625 31 17500 5000 31 140000 625 20 12500 Priority #5 312.5 36 10312.5 10000 36 330000 312.5 20 6250 Total Percentage of 10-MHz BUS 246562.5 2.5% (37.4% faster than S08) Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. 560625 5.6% (42.4% slower than S08) 393750 3.9% TM Use Cases в–єConclusion In the case that high priority interrupt with high frequency, the RS08 gets MORE efficient than S08 (37.4% faster in the example). вЂў In the case that high priority interrupt with low frequency, the RS08 gets LESS efficient than S08 (42.4% slower in the example). вЂў Less interrupts MORE efficient in RS08 вЂў The only assumption is, вЂў Вѓ No big task executed in background program Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM BACKUP Timebase Event Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Timebase Event Constant Time t в–є InfLoop: в–є wait в–є brset SIP1_RTI, MAP_ADDR_6(SIP1), TimeTick в–є brset SIP1_LVD, MAP_ADDR_6(SIP1), Brownout в–є в–є TimeTick: в–є ; ... Code here ... в–є jmp InfLoop в–є в–є Brownout: в–є ; ... Code here ... в–є jmp InfLoop Wait takes 3 bus cycles to wake up at most Brset takes 5 bus cycles At most 8 bus cycles software overhead At 10MHz bus, 0.8us required. Application Example Sensor applications, Low end power meter Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Timebase with additional Interrupt Handling Constant Time в–є InfLoop: wait в–є brset SIP1_IIC, MAP_ADDR_6(SIP1), _IIC_ISR в–є brset SIP1_SCI, MAP_ADDR_6(SIP1), в–є в–є _SCI_ISR brset SIP1_RTI, MAP_ADDR_6(SIP1), _TimeTick brset SIP1_LVD, MAP_ADDR_6(SIP1), Brownout _IIC_ISR: jmp IIC_ISR _SCI_ISR: jmp SCI_ISR _TimeTick: jmp TimeTick Brownout: ; ... Code here ... jmp InfLoop в–є в–є в–є в–є в–є в–є в–є в–є IIC_ISR: в–є ; ... Code here ... в–є jmp InfLoop в–є _SCI_ISR: в–є ; ... Code here ... в–є jmp InfLoop в–є в–є _TimeTick: в–є ; ... Code here ... в–є jmp InfLoop Asynchronous Interrupt t Software defines interrupt priority At 10MHz, IIC_SIR takes 1.2us to response (including JMP) SCI_ISR takes 1.7us to response (including JMP) Application Example Sensor applications, Low end power meter, mouse, home applicants, remote control Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Linear Coding Constant Time ISR execution t в–єIf you are forced to use linear code, i.e. CPU bandwidth is reaching 100%, pending interrupt can be checked in regular manner. Int_Check: MACRO tst beq jsr ENDM SIP1 *+5 Handle_interrupt Handle_Interrupt: brset SIP1_IIC, MAP_ADDR_6(SIP1), IIC_ISR brset SIP1_SCI, MAP_ADDR_6(SIP1), SCI_ISR brset SIP1_LVD, MAP_ADDR_6(SIP1), Brownout rts Brownout: ; ... Code here ... bra Handle_Interrupt IIC_ISR: ; ... Code here ... bra Handle_Interrupt SCI_ISR: ; ... Code here ... bra Handle_Interrupt Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM BACKUP Skills used in Demo Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Programming Skills in The Demo в–єInline вЂў Technology Inline ISR makes the RS08 program smaller and more efficient. в–єSoftware вЂў Software defined ISR priorities make RS08 program more flexible. Hardware defined ISR priorities are inhibited by the IC maker. в–єQuick вЂў defined ISR priorities Polling Mode Quick polling mode ensure that the interrupt with highest priority will be responded prior to the others. Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM BACKUP MISC Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM 9RS08KA2 вЂў Supply Voltage / Performance вЂў 1.8-5.5V 1K/2K SIM Flash Analog вЂў Core Comp вЂў Memory BDC 8-bit 63 bytes RAM ICS KBI RS08 Core COP Modulo Timer вЂў RS08 Core вЂў 1K / 2K bytes Flash вЂў 63 bytes RAM вЂў Analog Comparator вЂў Full rail-to-rail supply operation, can operate in STOP mode вЂў Features/ Benefits вЂў Computer operating properly feature (COP) вЂў Integrated Clock Source (ICS) up to 10MHz internal bus operation with 2% deviation over full temperature and voltage range вЂў 8-bit Modulo Timer вЂў 3 / 5 channel keyboard interrupt (KBI) вЂў LVD (low voltage detect) with reset or stop wakeup вЂў External Vpp required for Flash programming вЂў Auto wakeup вЂў Target Package вЂў 6 pin DFN, 8 pin narrow body SOIC, 8PDIP вЂў Development Tools/ Documentation вЂў Similar to existing S08 platform вЂў Target Applications: вЂў Small appliance, toys, simple analog comparator / simple logic replacement, HB-LED Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM A Typical Scheme of Timing Based Schedule Tasks Prioritized Tasks Status Next Status Next 2nd Status Dotted tasks will not be executed in current available interval Interrupt Interrupt Service Routine Task Priority Schedule Task schedule being executed Time Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM Freescale Semiconductor Proprietary Information. Freescaleв„ў and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. В© Freescale Semiconductor, Inc. 2008. TM