Introduction ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr. Filip Cuckov Overview 1. 2. 3. 4. Administrative Objectives Grading Schedule 1. Administrative • Professor • • • • • Dr. Filip Čučkov (Dr. Phillip CHOOCH-kohv, OR Dr. C) Office: Science Center, 3rd floor, room 111 Office Hours: Regular weekly and by appointment E-mail: [email protected] Phone: (617) 287-3539 • Catalog Description: The course will cover topics including tools and methodologies for top-down design of complex digital systems. Important topics include minimization, mixed logic, algorithmic state machines, microprogrammed controllers, creating and using a gold model, data and control path design, and data movement and routing via buses. Design methodologies covered include managing the design process from concept to implementation, gold model validation, and introduction to design flow. A hardware description language is used extensively to demonstrate models and methodologies, and is also used in design exercises and projects. 1. Administrative • Prerequisites: ENGIN 241 – Digital Systems with Lab • Textbooks: • Charles H. Roth Jr. and Lizzy K. John, Digital Systems Design Using VHDL, 2008 ISBN-13: 9780534384623 (Publisher Link) (Amazon) • Reference: B. Mealy, F. Tappero, Free Range VDHL, freerangefactory.org, 2013 Complementary download at http://freerangefactory.org/books_tuts.html • Website(s): http://eng.umb.edu/~cuckov/classes/engin341 http://umb.umassonline.net/ (BlackBoard) 1. Administrative - Honor Code • All work is individual. • Give credit where credit is due. • Cheating will not be tolerated. • There will be no second chances. I pledge to uphold the governing principles of the Code of Student Conduct of the University of Massachusetts Boston. I will refrain from any form of academic dishonesty or deception, cheating, and plagiarism. I pledge that all the work submitted here is my own, and that I have clearly acknowledged and referenced other people’s work. I am aware that it is my responsibility to turn in other students who have committed an act of academic dishonesty; and if I do not, then I am in violation of the Code. I will report to formal proceedings if summoned. 2. Objectives Course Learning Objectives: • Develop proficiency in modeling and digital systems with VHDL • Understand mixed logic design, flip-flop design, SOP and POS forms, and state minimization • Design using algorithmic state machine methods • Controller design using structured design approaches including one-hot and microcoded controllers • Modeling datapath components including registers, counters, ALUs • Create datapath to model complex digital systems • Control path design • Introduction to FPGA design flow • Introduction to system modeling flow and tools 2. Objectives - Topics Covered 1. 2. 3. 4. 5. 6. 7. 8. 9. Review of Logic Design Fundamentals Introduction to VHDL Introduction to Programmable Logic Devices Design Examples State Machine Charts and Microprogramming Designing with FPGAs Floating-Point Arithmetic Additional Topics in VHDL Design of a RISC Microprocessor 3. Grading • 10 % Homework Assignments • 2 Homeworks • Each worth 5% • 90 % Labs • Labs 1-7 • Each worth 10% • Labs 8 and 9 • Worth 20% but require only one lab report • Demo required during final exam time • Each lab graded on the following scale: • 60% Lab Completion • May include preliminary work or demonstration • 40% Lab Report • Must follow required format 4. Schedule Date Class Lecture Assignment Due Reading Assigned 9/8/2015 1 9/15/2015 2 9/22/2015 3 9/29/2015 4 10/6/2015 5 10/13/2015 6 10/20/2015 7 10/27/2015 8 11/3/2015 9 11/10/2015 10 11/17/2015 11 Introduction and Digital Systems Design Overview VHDL - Dataflow and Structural Modeling, Testbenches VHDL - Processes, Data Types and Operators, Synthesis VHDL - Behavioral Modeling and Registered Elements ASM Charts, Minimization and Microporgramming Floating Point Arithmetic Standard System Interfacing and Comm. Protocols VHDL - Functions, Procedures and Libraries VHDL - System and Memory Modeling VHDL - Advanced Tesbenches Hardware Testing and Design for Testability 11/24/2015 12 12/1/2015 13 12/8/2015 14 RISC Microprocessor Design - ISA L7 Report RISC Microprocessor Design - Datapath and Controller RISC Microprocessor Design - Testing and Validation Final Exam Demonstrations of MIPS Processor HW 1 L1 Report L2 Report L3 Report L4 Report HW 2 RJ: (3,6), 2.3, 2.4 FR: 2, 3 RJ 2.5-2.7, 2.10-2.13 RJ 2.8, 2.9, 2.14-2.19 RJ 1.9, 5 RJ 7 RJ 11.3 RJ 8 RJ 11.2 L5 Report RJ 10 L6 Report Final (L8+L9) Rep. Map: RJ - Roth and John Textbook, FR - Free Range VHDL Textbook, (Light Reading) Lab Concepts Practiced 1 2 3 4 5 6 7 8 9 10 11 Exercise FPGA Design Flow L0 - Design Flow VHDL Structural Modeling and Functional Simulation L1 - Modular Design and Testbenches Simple combinational circuit design L2 - ALU Design Simple sequential circuit design L3 - Hexadecimal Counter Algorithmic State Machines L4 - Traffic Light Controller Datapath/Controller Design and SPI Communication L5 - Standard Peripheral Interfacing Using Block RAM in FPGAs L6 - Stack Calculator Understanding BIST and JTAG L7 - Memory Built-In Self Test 12 13 Text I/O in VHDL 14 Microprocessor Design L8 - MIPS Processor 1 L8 - MIPS Processor 1 L9 - MIPS Processor 2
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