Control IC for High Efficiency DC

Panasonic Technical Journal Vol. 58 No.1 Apr. 2012
Control IC for High Efficiency DC-DC Converter
省エネ電源制御ＩＣ
Takuya Ishii
石井卓也
Abstract
Efficiency of DC-DC converter is dependent on the performance of the main devices, such as the switching transistor, for
instance. So a control IC which has drivers for switching transistors is required to drive them optimally. The hysteretic control
DC-DC converters for Point of Load (POL) have 2 Trench Metal Oxide Semiconductor-Field Effect Transistor
(TMOS-FET) chips and a control IC chip in the same Multi-Chip Package (MCP). The control IC reduces the fluctuations of
switching frequency and output ripple voltage, which are demerits of hysteretic control. The test result shows 3% higher
conversion efficiency than conventional converter under the condition of rated output power (3 A).
要
旨
電源回路の高効率化は，スイッチングトランジスタ等の主要デバイスの性能によるところが大きい．制御 IC はスイッチ
ングトランジスタの駆動回路部を有し，好適に駆動することが求められる．開発した NN3019x 及び NN3031x は，スイッチ
ングトランジスタに TMOS-FET を用いて高効率化したヒステリティック制御方式の POL（Point of Load）用 DC-DC コンバ
ータであり，2 チップの TMOS-FET と制御 IC チップを同一パッケージに実装した MCP（Multi-Chip Package）構造を有する．
搭載した制御 IC は，ヒステリティック制御方式の課題であったスイッチング周波数の変動や出力リップル電圧の増加を抑制
できる．測定結果では、定格出力 3A において同等他社製品に比べて効率が約 3%向上した。
1. Introduction
several MHz by switching operation of main switch Q1, and
Power circuit is essential for almost all electronic devices, so
rectified and smoothed by inductor L, rectifier switch Q2, and
improving its conversion efficiency is a key technical issue
output capacitor C to produce output DC voltage Eo. Rectifier
prior to recent energy saving requirements. Most DC-DC
switch Q2 is a switching transistor which is turned ON/OFF
converters, each of which is a minimum unit constituting a
alternately with main switch Q1. Defining the switching period
power circuit, have a high efficiency of more than 90%, but
and ON time of main switch Q1 as Ts and Ton respectively, the
further improvement is required.
ideal relationship between input and output voltages is shown
Basically, DC-DC converter consists of main switch and
rectifier switch (or diode), inductor, output capacitor, and
control circuit. Most of the losses at power conversion are
induced by main switch, rectifier switch, and inductor.
Field-effect
transistor
with
Trench
Metal
Oxide
Semiconductor structure (TMOS-FET) has been developed as a
switching transistor for main and rectifier switches. This paper
introduces a DC-DC converter for POL with Multi-Chip
Package (MCP) structure, which includes TMOS-FET and
control IC in the same package.
2. Buck Converter
2.1 Basic Operation of Buck Converter
Fig. 1 illustrates circuit configuration and operating
waveform of a DC-DC converter called buck converter. Input
DC voltage Ei is converted to a pulse voltage of tens of kHz to
as the equation (1). The control circuit adjusts the ON/OFF
Panasonic Technical Journal Vol. 58 No.1 Apr. 2012
times of main switch Q1 and rectifier switch Q2 so that output
DC voltage Eo is stabilized to the desired value.
Eo 
Ton
 Ei
Ts
･･･････････････････････(1)
2.2 Loss of Switching Transistor
The loss of switching transistor falls roughly into two types:
switching loss and conduction loss. Fig. 2 shows losses of
switching transistor.
Switching loss means a loss produced when transistor is
turned ON or OFF, which corresponds to the losses P1 and P2
for the periods Tr and Tf in the figure. It increases as switching
frequency increases. In order to reduce switching loss,
switching periods (Tr, Tf) should be shorten by eliminating
parasitic capacitance of switching transistor and by increasing
instantaneous drive current of the control circuit.
Conduction loss is represented as the product of voltage and
switching transistor. When specifying drive conditions, it is
current during the ON period of switching transistor (the period
important to consider a loss reduction on the entire DC-DC
excluding Tr and Tf in the figure). In order to reduce
converter.
conduction loss, ON resistance of switching transistor should
be reduced and gate voltage as a drive capacity should be
3. DC-DC Converter for POL
increased.
Table 1 lists the POL DC-DC converters we have developed.
In addition, for the region of high switching frequency, care
POL is a DC-DC converter which is to be located near the load
must be taken to minimize loss during dead time (Td1 and Td2
(LSI) and supplies low voltage and large current. Consumption
in the figure). Dead time is a period used to prevent main
current of LSI largely varies with its operation mode for saving
switch from turning ON simultaneously with rectifier switch,
power, so POL DC-DC converter is demanded not only to be
during which both switches are OFF, so a current flows to the
small and high efficient but also to have fast response to reduce
body diode of the switch. For this reason, conduction loss
fluctuation of power supply voltage due to a sudden change of
increases even in a short period as the product of forward
supply current.
voltage and current of the body diode. Therefore, dead time
It features the following:
must be minimized.
・Low loss with TMOS-FET
Increasing drive current or gate voltage causes drive loss of
・Coming in newly-developed small multi-chip QFN (Quad Flat
the control circuit to be increased. In other words, there is a
Non-leaded) package
trade off between this phenomenon and reducing loss of
・Fast response with hysteretic control
第１表 POL_DC-DC コンバータラインナップ
Table 1 Line-up of POL_DC-DC converters
Low Voltage input Type
制御ＩＣ
入力電圧
NN30194A
No.1
出力電流
Middle Voltage input Type
NN30196A
No.3
NN30310A
No.4
0.6 to 3.5V
3A
6A
NN30311A
No.5
NN30312A
No.6
4.5 to 28V(VIN/PVIN)
4.5 to 5.6V(VIN) / 2.9 to 5.6V(PVIN)
出力電圧
オ主SW
ン
抵
抗整流SW
NN30195A
No.2
0.75 to 5.5V
9A
3A
6A
10A
25m Ω
25m Ω
9m Ω
25m Ω
9m Ω
25m Ω
HQFN24
HQFN40
HQFN24
HQFN40
縦横
4x4 ㎜
6x6 ㎜
4x4 ㎜
6x6 ㎜
高さ
0.5 ㎜
0.5 ㎜
0.5 ㎜
0.5 ㎜
SW周波数
パッケージ
0.5 / 1 / 2MHz
9m Ω
9m Ω
0.25 / 0.75 / 1.25MHz
Panasonic Technical Journal Vol. 58 No.1 Apr. 2012
3.1 Low Loss with TMOS-FET
Conduction loss of main switch (Pon1) and conduction loss
of rectifier switch (Pon2) are represented as the following
equations by defining their ON resistances as Ron1 and Ron2.
Pon1 
Eo
 Io 2  Ron1
Ei
･･････････････････(2)
Pon 2 
Ei  Eo
 Io 2  Ron 2
Ei
･･････････････････(3)
The ON resistance of TMOS-FET is 8 mΩ/mm2, almost half
of previous FET[1]. As shown in Table 1, ON resistance is set
to 9 mΩ for large output use. In particular, when input voltage
is high, conduction loss at the rectifier switch side increases as
shown in the equation (3), so ON resistance is set to 9 mΩ
even for 6A model. These ON resistance values are almost half
of those of a competitor's product, thus improving the
efficiency at heavy load as shown in Fig. 3.
3.3 Hysteretic Control[2], [3]
In basic hysteretic control method, main switch is turned
ON/OFF so that output voltage varies within a given range as
As expected, it is impossible to achieve high efficiency
shown in Fig. 5. Unlike normal control method, the hysteresis
superior to that of a competitor's product in all load levels, but
comparator output turns main switch ON/OFF, thus enabling
setting ON resistance high allows the efficiency in middle load
fast response with no analogous phase compensation and
level to be improved although efficiency in heavy load level is
response delay.
deteriorated.
On the other hand, a ripple voltage corresponding to
hysteresis width of the comparator is output. This voltage is a
voltage drop produced through an ESR (Equivalent Series
Efficiency (%)
100
95
NN30310
No.4
Ron1=25mΩ
Ron2=25mΩ
f=750kHz
Competitor
Ron=120mΩ
Ron2=70mΩ
f=700kHz
Resistance) and is desired to be small. Output ripple voltage
can be reduced by decreasing hysteresis width ∆V, however,
causing switching frequency to be high or its operation to be
90
unstable.
Control ICs we have developed employ a way to add a ramp
85
80
Condition
Vin=12V,Vout=3.3V
75
70
0
1
2
3
4
5
Load current (A)
第３図効率特性
Fig.3 Efficiency comparison
3.2 Multi-Chip Package
Fig. 4 gives external appearance of QFN package in which
the POL DC-DC converter is mounted. In this package, 2
TMOS-FET chips (main switch and rectifier switch) and
control IC are included. As shown in Table 1, these chips are
placed in the space of 6 mm x 6 mm, reducing mounting space
by approximately 12 mm2 compared to conventional models
that have switching transistor and control IC in separate
packages.
Panasonic Technical Journal Vol. 58 No.1 Apr. 2012
wave equivalent to output ripple voltage to the reference
3.4 Driver Block
voltage that is used to compare with output voltage, so as to
Fig. 7 depicts the driver block. TMOS-FET used in main
ensure hysteresis width while decreasing output ripple voltage.
switch Q1 is an N-channel type with low ON resistance, so
In addition, by setting the ON time of main switch to a given
requires a bootstrap circuit to ensure the drive supply voltage
value, fluctuation of switching frequency has been reduced.
based on the voltage on LX pin. This control IC needs a drive
Their typical circuit configuration and operating waveform are
capacitor Cbst between BST and LX pins, but has a built-in
shown in Fig. 6.
charging circuit Dbst to charge it.
In the figure above, double line and broken line indicate the
The circuit block LGO detects that the gate voltage of
ranges for control IC and MCP, respectively. By a hysteresis
rectifier switch Q2 is lower than the threshold voltage or that
comparator the output detection voltage Vfb, which is detected
Q2 is OFF. In normal operation, main switch Q1 is turned ON
through a resistive divider, is compared to the reference voltage
as described in the following procedure: (1) output detection
Vr to which a ramp wave is added. Actually, the input offset of
voltage Vfb and reference voltage Vr match. (2) comparator is
hysteresis comparator is ramped so that the output detection
reversed (3) gate voltage of rectifier switch Q2 decreases to
voltage Vfb is compared to the reference voltage Vr to which a
less than the threshold voltage (4) LGO output is reversed (5)
ramp wave is added, thus saving circuit scale and consumption
gate voltage of main switch Q1 increases. Similarly, rectifier
current. When the output detection voltage Vfb equals the
switch Q2 is turned ON after HGO detects that main switch Q1
increasing reference voltage Vr while main switch Q1 is OFF,
is turned OFF. Consequently, main switch Q1 and rectifier
the comparison result Vc is reversed and main switch Q1 is
switch Q2 are prevented from turning ON simultaneously and
turned ON. At the same time, a Ton timer used to set ON time
dead time is minimized.
counts ON time, and main switch Q1 is turned OFF after the
ON time that is set with I/O voltages elapses. The ON time Ton
is specified as the equation (4) using the virtual period Tsi. In
combination with the equation (1), we can find the actual
switching period Ts is nearly equal to the virtual period Tsi.
Ton 
Eo
 Tsi
Ei
･････････････････････(4)
3.5 Light Load Operation
The equation (1) is valid during CCM (Continuous
Conductive Mode) in which inductor current is always flowing.
For DCM (Discontinuous Conductive Mode) that includes a
period of inductor current = 0 due to light load, Ton/Ts must be
decreased to ensure output is stabilized. The ON time Ton of
this control IC does not depend on load, so at light load
OFF-time is extended and switching frequency fs decreases in
proportional to output current Io as shown in the equation
below.
fs 
2Eo  Io  L
Ei  Ei  Eo   Ton 2
･･････････････････(5)
The lighter the load, the lower the switching frequency, thus
Panasonic Technical Journal Vol. 58 No.1 Apr. 2012
reducing switching loss. As indicated in Fig. 3, our products
References
have a high efficiency equal to or superior to that of a
competitor's product under the condition of output current of
0.1 A.
[1] "New Trench MOS FET," TECHNO-FRONTIER2010, Exhibition
panel
[2] Katsumi Yamashita, "Leading the Way in High-Speed Hysteresis
4. Summary
We have developed POL (Point of Load) DC-DC converter
with high-efficiency hysteretic control using TMOS-FET
switching transistor. This DC-DC converter allows power supply
to be smaller and more efficient. With this technology, we will
Control of Power Supply," 6th Analog Enhancement Seminar
(Analog Kyoka-jyuku), Nikkei Electronics, no. 15, June 2009, pp.
78-86
[3] "Fast Response Hysteretic DC-DC Converter,"
TECHNO-FRONTIER2010, Exhibition panel
develop new DC-DC converters, and further improve the
performance of control IC to ensure lower power at standby,
Introducing the writer:
higher switching frequency, and smaller size. To make power
consumption at standby lower, control IC must resume from
Takuya
standby faster. To make switching frequency higher, delay times
Application Specific Standard Products Business
Unit, Semiconductor Business Group, Industrial
Devices Company
of each circuit block of the driver described in this paper must be
shortened to further reduce dead time.
Ishii
石井
卓也

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