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Problem Set No. 1 - Logic Functions and Boolean Algebra
1. Use Boolean algebra or otherwise to show that if
Y = A·B ·C ·D+A·B ·C ·D+A·B ·C ·D+A·B ·C ·D+A·B ·C ·D+A·B ·C ·D
then
Y =A·C ·D+B·C ·D+A·B·D+A·B·D
2. Use Boolean algebra or otherwise to show that if
Q=A·B·C ·D+A·B·C ·D+A·B·C ·D+A·B·C ·D
then
Q=A·C +A·C +B·D+B·D
3. Implement the logic expression
D = A · (B + C) + B · C + A · B
using only NAND gates and draw the circuit diagram.
4. Use Karnaugh map or otherwise to simplify the following logic function.
f =A·B·C +A·B·C +A·B·C +A·B·C
5. An investor proposed the following technique to make money in the stock market:
1. If the dividends paid on a stock exceed those paid on a bond, buy the stock.
2. If the dividends paid on a bond exceed those paid on a stock, buy the bond unless
the growth rate of the stock is at least 25 percent per year for the past 5 years,
in which case the stock should be purchased.
The investor required a special-purpose computer to tell her what to buy. The computer requires three switches: for higher dividend in stock, high dividend in bond, and
25 percent growth rate; and two lamps, one to light if a stock is selected and the other
to light if a bond is selected. Design the computer using all-NAND logic.
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6. For the logic circuit of Figure Q6,
(a) derive a logic expression for the circuit,
(b) convert the logic expression in Part (i) to product-of-sum form, and
(c) convert the logic expression in Part (i) to sum-of-product form.
A
B
·
e
¸
·
C
¸
·
B
©
»
ª
e
¼
¸
C
Figure Q6
7. Write the logic equation for the Karnaugh map shown in Figure Q7.
@ AB
@
CD @ 00
00
01
1
11
1
01
11
10
1
1
1
10
1
1
1
Figure Q7
8. An important part of the central processor of any computer is the arithmetic unit
in which binary addition, subtraction, division and multiplication are carried out.
Subtraction, however, can be preformed by adding complementary numbers. Multiplication can also be performed by repeated addition. Division can be achieved by
repeated subtraction. This makes the adder the centrepiece of the arithmetic unit.
Half Adder
This is a circuit capable of adding two bits. It has two inputs and two outputs. The
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operation of a half adder can be expressed in the form of a truth table, as shown below.
Inputs Outputs
A
B
S
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
where A and B are two one-bit binary numbers. S is the sum and C is the carry. Use
only NAND circuits to implement the half adder.
Full Adder
A half adder is not useful on its own, and a third input is often required for carries.
An adder with three inputs and two outputs is called a full adder. The truth table for
a full adder is given below:
Inputs
Outputs
A
B
Ci
S
Co
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
where Ci is the carry-in from the previous addition and Co is the carry-out to the next
addition. Design the full adder (1) by any logic circuits, and (2) by using half adder
and/or any logic circuits.
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9. A ripple counter is shown in Figure Q9. Sketch the waveforms of A, B, and C for a
period of 8-input clock pulses. Assume that all flip-flops are initially reset.
A
B
C
JA
1
Q
u
JB
1
e
1
Q
u
1
e
KA
Q
1
JC
Q
KC
Q
e
KB
Q
1
Figure Q9
10. A divide-by-three ring counter is shown in Figure Q10. Sketch the timing diagrams
of the three outputs A, B, and C for a period of 6 complete clock pulses. You may
assume that the 3 outputs are initially in “0” states.
-
D
A
-
D
B
A
Clock
-
D
C
B
6
u
6
u
-
C
6
Figure Q10
11. Design a synchronous sequential generator, using three JK flip-flops and any necessary
logic gates, to count the sequence 2, 4, 6, and 0 when the control line D is logic 0, and
count the sequence 0, 6, 4, and 2 when the control line is at logic 1. Should the circuit
fall into a disallowed state, it should always return to the 0 state.
In your answer, you should include:
(a) a state table,
(b) an excitation table,
(c) simplified Boolean expressions, and
(d) the complete circuit design.
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12. Using JK flip-flop and any combinational logic gates, design a synchronous sequential
generator to count the sequence 002 to 112 and repeat.
In your answer, you should include:
(a) a state table,
(b) an excitation table,
(c) simplified Boolean expressions, and
(d) the complete circuit design.
13. Design a mod-6 up down synchronous counter by using D-type flip-flops as memory
elements. A single control line determines the direction of the count. With the control
line LOW the count is down and the control line HIGH the count is UP. Clearly show
your design procedure and draw the complete circuit of your design.
14. For the clock and data waveform shown in Figure Q14, draw the output waveform Q
for a D-type flip-flop for each of the following types of triggering:
(a) positive edge triggered.
(b) negative edge triggered.
Assume that Q = 0 initially.
Clock
Data
Figure Q14
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15. Figure Q15 shows the logic diagram of a 4-stage self-starting ring counter. Complete
the following state table.
¶¨
e
µ§
D1
u
Q1
D1
e CLK
Q1
e CLK
Q1
CLK
u
D1
e CLK
Q1
u
u
Q1
u
D1
e CLK
Q1
Q1
pu
Figure Q15
Present states
Next States
Q1
Q2
Q3
Q4
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Q01
Q02
Q03
Inputs
Q04
Q1
D1
D2
D3
D4
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16. Design a voting machine so that its output is “high” indicating when a majority of
four inputs is true.
17. Figure Q17 shows a simple diagram of a conveyor system. The electric motor powering
the conveyor to move material is to be turned on when one of two operators is in
position, if material is present to be moved and if the protective interlock switch is not
open. Input and output variables are to be expressed in binary; that is, if operator 1
is in position then the associated variable is logical 1. The motor is on if its output
control variable is a 1, and the motor is off if the variable is a 0. Design the control
circuit for the conveyor system.
Figure 1: Conveyor system for Q17
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18. A conveyor system brings raw material in from three different sources. The three
sources converge into a single output conveyor. Sensors mounted adjacent to each
source conveyor indicate the presence of raw material. All four conveyors have separate
motors so they can individually controlled. Each source conveyor can have a different
speed. The output product flow rate is fixed ; it can be turned only on or off. The
output product rate must match the source flow rates. To accomplish this the following
conditions must be met. If source 1 has product, then sources 2 and 3 or both can
be turned on. In the event that no product is available from the three sources, the
output conveyor must be turned off. If no product is available, the respective source
conveyor must be turned off.
Design the control circuit for the conveyor system.
Figure 2: Conveyor system for Q18