2.4 Computer Buses
Bus Arbitration
1- Centralized Arbitration
Three types:
-
A single shared bus request Line
Bus Request
Bus grant may or
may not be
propagated along
the chain
Figure 2.15: A centralized one-level bus arbiter using daisy chaining
-
Uses Single bus request line
When the central arbiter detects that the bus request line is one it will issues a
grant by setting the bus grant line to 1.
- The bus grant line is connected to all I/O devices in series (daisy chained).
- When the device physically closest to the arbiter sees the grant signal, it will
take it and will not propagate the grant signal to the nest device if it made a bus
request. Otherwise, it will pass the signal to its neighbor, which will repeat the
same process and so on until the some device accepts the grant and takes the bus
Advantage
Easy to implement and inexpensive because it needs only two control lines independent
of the number of I/O devices connected to the bus.
Disadvantages
1234-
Priorities are fixed ( device 1 > 2 > 3 >4)
Devices nearer to the arbiter have higher priorities than those which are far away.
Arbitration time increases as number of devices increases
Not fault-tolerant (if the arbiter failed, the whole system will fail)
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- Multiple shared bus request but with different priority levels
Figure 2.16: A centralized two-level bus arbiter using daisy chaining
-
For each priority level there is a bus request line and a bus grant line.
Each device is attached to one of the bus quest levels, with devices that need
higher priorities (time-critical) attached to the higher priority request levels.
If more than one request is made at the same time, the arbiter issues a grant
signal to the highest priority request line only.
If more than one request is made on the same priority level, then daisy
chaining is used.
For the above figure (2.16), if bus request level 1 has higher priority than bus
request level 2 then the device priorities will be (1 > 2 > 4 > 3 > 5)
- Independent bus request lines
1
2
3
4
Figure 2.17: A centralized bus arbitration with independent bus request and grant lines
-
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This configuration is used in PCI bus.
Each device has its own bus request and bus grant lines.
Arbiter can apply several priority policies for the devices.
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Advantages:
-
faster Arbitration time than the shared bus request
Better fault-tolerance than the shared configuration
Arbiter can apply several priority policies for the devices.
Disadvantages:
-
Complex and expensive to implement
Number of control lines is proportional to the number of hosts
2- Distributed Arbitration
Figure 2.18: Distributed arbitration
In this configuration there is no bus arbiter. All devices waiting to use the bus have equal
responsibility in carrying out the arbitration process without using a central arbiter. Each
device has its own bus request line. Any I/O device is also connected to all bus request
lines of other devices in order to read them.. Bus request lines are assigned priorities
usually from 0 to 15. When a device wants to use the bus, it sets its bus request line to 1.
All devices can read the request lines, so when the bus becomes free, each device knows
whether it was the highest priority requester, if yes, it can use the bus otherwise it has to
wait until all the higher priority requester finish using the bus.
This type of arbitration is used in SCSI bus.
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Advantages
-
Less cost because no arbiter exists
Offers higher reliability than centralized arbitration because operation of the
bus is not dependent on any single device. (Fault-tolerant).
Disadvantages
-
Priorities are fixed
Possibility that some devices with low priority levels might not be able to use
the bus for long time (starvation)
Requires many bus lines
Number of devices is limited to the number of priority request lines in the bus.
Example buses
Figure 2.19: Architecture of an early Pentium system. The thicker buses have more
bandwidth than the thinner ones but the figure is not to scale
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Figure 2.20: The bus structure of a modern Pentium 4. Note the location of AGP bus
Figure 2.21:The PCI Express bus
Figure 2.22: USB bus tree structure
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