Mixed PLB and Interconnect BIST
for FPGAs Without Fault-Free
Assumptions
Vishal Suthar and Shantanu Dutt
Electrical and Computer Engineering
University of Illinois at Chicago.
Outline
The problem of fault-free assumptions & other
stories
Iterative Bootstrapping (IB) – A general solution
Mixed BIST: Combining PLB & interconnect
testing with IB—no fault-free assumptions
– Recent work in PLB BIST (HD-BIST)
– Recent work in interconnect BIST (I-BIST)
Simulation Results
Conclusions
Built-In Self-Test in FPGAs—Basic Concepts
Comparison based BIST:
TPG - Test Pattern Generator
ORA - Output Response
• In each session diff. PLBs act as CUTs,
Analyser
TPG and ORA.
CUT - Cells Under Test
WUT - Wires Under Test
TPG
CUT
WUT
CUT
WUT
ORA
Pass / fail
Gross syndrome (GS):
The gross syndrome of a session
is the overall fail/pass (X/√ ) result of a
session.
Match in all CUT outputs =>
ORA output = 0 => GS = pass (√ )
Else ORA output = 1 => GS = fail (X)
Drawbacks in deterministic BIST techniques
BISTer-1: (V. Verma, S. Dutt, V. Suthar, DAC 2004)
A
TPG
D
ORA
A
ORA
D
CUT
A
CUT
D
CUT
A
CUT
D
TPG
CUT
CUT
TPG
CUT
ORA
TPG
CUT
ORA
B
C
B
C
B
C
B
C
(S1)
(S2)
(S3)
(S4)
Fault coverage (%)
BISTer-1
Fault coverage (%)
Theorem: BISTer-1 is 1/4 diagnosable
BISTer-0
100
90
80
70
60
50
40
1
2
5
7
10
15
20
25
30
Fault density (%)
(a) Random faults
35
40
BISTer-1
BISTer-0
100
90
80
70
60
50
40
30
8.8 (1)
16.9 (2)
26.6 (3)
Fault density (cluster density) (%)
(b) Clustered faults
Fallacy of Fault-Free Assumptions
1. Limited / Incorrect diagnosability in presence of multiple faults
in the BISTer area.
Unrealistic assumptions: a) The test circuit (TPG & ORA) is fault-free.
b) No fault masking; c) no more than 1-2 faults in BISTer area
BISTer
CUT
ORA
TPG
GS= pass
(non-det.)
GS= fail
(false +ve)
CUT
2. Absence of BIST techniques that can diagnose faults present in
PLBs as well as interconnects.
Unrealistic assumption: while testing PLBs the interconnects used in the
BISTer area are fault-free and similarly, while testing interconnects the PLBs
forming the test circuit are fault-free.
Iterative Bootstrapping (IB)
Need: An ability to detect and diagnose faults in presence of multiple faults
and/or clustered fault patterns in both PLBs and interconnects, with
high probability.
Solution: Iterative bootstrapping for obtaining fault-free test circuits
(w/ fault-free PLBs & interconnects)
Test circuit Ti with f-free prob. = qi
Use redundancy (e.g. TMR) to increase qi
Test PLBs conf. for ORA and TPG functions
& reqd. interconnects using T
i
o/p = Test circuit
Test circuit
Ti1 with f-free prob.
qi  1  qi
Ti  Ti 1
No
qi  1  qthres
Yes
Final test circuit
Iterative Bootstrapping (IB)
• Does it always work? No
• If not, are there conditions under which it works?
• Are these conditions realistic? Yes
Yes
• Consider TMR as the redundant circuit: p = prob. of a faulty PLB,
q1 (q2) = prob of fault-free TMR TPG/ORA (1 PLB impl.) in 1st (2nd) iter of IB
•
• Theorem: If prob. of correct oper. f(q) [q=fault-free prob. of component]
is monotonically non-decreasing, and f(q0=1-p) >= 1-p, then IB provides
us w/ s sequence of redundant test circuits with monotonically nondecreasing fault-free probabilities q1, q2, ….., qk.
Mixed PLB and Interconnect BIST
•
Two high-diagnosability BIST techniques used.
1. HD-BIST (High-Diagnosability BIST) – PLB testing [GLSVLSI’05]
2. I-BIST (Interconnect BIST) – Interconnect testing [DATE’06]
•
Reqmt for reliable mixed testing w/ faults in PLBs & interconnects:
PLB testing
requires
obtained from
F-free TPGs/ORAs
F-free interconnect
obtained from
requires
Interconnect testing
• A classic chicken-&-egg problem (which comes first).
• Solution: Break the cycle via Iterative Bootstrapping
Mixed PLB and Interconnect BIST (contd)
• Solution: Break the cycle via IB and then interleave the various stages
of HD-BIST and I-BIST so that fault-free components (w/ high prob.) are
available to test the next stage.
Our approach:
First phase – IB w/ TMR
Fault state unknown
test ckt. rqd. for phase
Non TMR’ed
Phase
Pi
Pi
test ckt. rqd. for phase
Pi 1
Mixed-BIST: PLB BIST Stages
HD-BIST [Suthar & Dutt, GLSVLSI’05]
START
Tester Stick
TPGORATPG
D E
F
TPG ORATPG
D E
F
TPG ORATPG
D E
F
CUT CUT TPG
A B C
TPG CUT CUT
A B C
CUT TPG CUT
A B C
Testee Stick
TPG shuffling scheme
(instead of TMR)
to reduce test vector
skipping probability
Theorem:
Pshuffled
Ptpg
p
Pshuffled  p  Ptpg
= prob. of shuffled TPG skipping
a test vector.
= prob. of normal TPG skipping
a test vector.
= prob. of a PLB being faulty.
Bootstrapping phases (2)
o/p = fault-free
ORA / stick (if exists)
Global testing – Fault detection
& gross diagnosis phase
o/p = suspect PLBs &
fault-free sticks
Detailed testing: Adaptive
diagnosis phase
o/p = faulty PLBs
END
HD-BIST Experimental Results
• HD-BISTer is compared with previous best online BIST techniques:
STAR BISTer proposed by [M. Abramovici et. al., ITC’00] and BISTer-1
• HD_3 -> HD-BISTer with TPG shuffling
HD_1 -> HD-BISTer without TPG shuffling.
FAULT COVERAGE:
Clustered faults
HD_3
100
HD_1
90
BISTer-1
80
70
STAR
60
50
40
1
2
5
F a u lt c o v e ra g e (% )
F a u lt c o v e r a g e (% )
Random faults
7 10 15 20 25
Fault density (%)
100
HD_3/1
90
80
BISTer-1
70
60
50
STAR
40
30
8.8
16.9
26.6
(1.0)
(2.0)
(3.0)
Cluster density (%)
Mixed-BIST: Interconnect BIST Stages
I-BIST [Suthar & Dutt, DATE’06]
Global Testing (1/5 configs)
Test vector 1:
Test vector 2:
Test vector 3:
0
1
0
1
0
0
0
1
0
1
0
0
n3 n2 n1
Approach:
1. Global Testing: First isolate the
possible fault locations to a small set of
interconnects in very few configurations
-> Suspect Set
2. Detailed Testing: Then diagnose
interconnects of suspect set for faults
using divide-&-conquer and in the final
iteration by comparison to known faultfree interconnects
A(n1, n2)
0
1
0
1
0
0
l 3 l 2 l1
A(l1, l2 )
A(n2 , n3 )
O(n1,l1)
O(n2, l2 )
Spanning
Switch
Stuck-closed
I-BIST: Results
Theoretical Results:
• Theorem: I-BIST has 100% guaranteed fault detectability
in the presence of multiple faults – a first
• I-BIST has the fewest configurations—5—per WUT-set
in global testing
• I-BIST has the fewest # of test vectors—3—per WUT-set
testing phase
Empirical Results:
Fault coverage (diagnosability) versus fault density
Mixed-BIST– Summary of Techniques
Our Mixed-BIST (M-BIST) approach attempts to
significantly reduce these negative effects via
– a careful application of iterative bootstrapping
– interleaving of various stages of I-BIST and HD-BIST
First phase – IB w/ TMR
Non TMR’ed
Test ckt. rqd. for phase P
i
Phase
Pi
Test ckt. rqd. for phase
Pi 1
Mixed BIST: Combining & Interleaving IB, I-BIST & HD-BIST
Interconnect global testing: test {s tracks / (r < s < t)} using TMR
NO
TMR’ed
r fault-free tracks found ?
YES
PLB bootstrapping: detect {IO-FF sticks} using r ff tracks
Interconnect global testing: test {(t - s) tracks} using IO-FF set
o/p = T-FF -> {ff tracks}
non-T-FF -> {suspect tracks}
PLB bootstrapping: detect {ff ORAs / stick} using T-FF set
o/p = ORA-FF -> {ff ORA PLBs}
Interconnect detailed testing
PLB fault detection and adaptive diagnosis
o/p = I-FF -> {ff interconnects} non-I-FF -> {faulty interconnects}
o/p = PLB-FF -> {ff PLBs} non-PLB-FF -> {faulty PLBs}
Non TMR’ed
o/p = IO-FF and non-IO-FF sticks
Simulation Results – Fault Coverage
• Comparison of PLB and interconnect testing in
M-BIST (without fault-free assumptions) v/s
HD-BIST (with fault-free assumptions) &
I-BIST (with fault-free assumptions)
Fault coverage – random faults
M-BIST v/s HD-BIST (w/ f-free assumptions)
Without fault-free assumptions
M-BIST v/s I-BIST (w/ f-free assumptions)
Without fault-free assumptions
With fault-free assumptions
100
99.5
2 % difference
99
98.5
98
F ault coverage (% )
100
Fault Coverage (%)
With fault-free assumptions
99.5
1.5 % difference
99
98.5
98
97.5
97.5
1
2
3
4
5
6
7
Fault density (%)
8
9
10
1
2
3
4
5
6
7
F ault density (% )
8
9
10
Simulation Results – False Positives
False positives – fault-free components incorrectly diagnosed as faulty.
-- measured as a percentage of faults inserted.
False positive results – random faults
M-BIST v/s HD-BIST (w/ f-free assumptions)
M-BIST v/s I-BIST (w/ f-free assumptions)
Without fault-free assumptions
With fault-free assumptions
40%
45.00
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
False positives (%)
False positives (%)
Without fault-free assumptions
With fault-free assumptions
5%
1
2
3
4
5
6
7
Fault density (%)
8
9
10
200%
200
180
160
140
120
100
80
60
40
20
0
0%
1
2
3
4
5
6
7
Fault density (%)
8
9
10
Conclusions
Goal: Mixed PLB and Interconnect BIST that does not
require any fault-free assumptions in order to:
– improve diagnosability and reduce false positives
– in the presence of clustered and high density faults in both PLBs
and interconnects
Introduced the novel concept of general iterative
bootstrapping for this purpose that can be used in
different test and fault tolerance domains
Analyzed the mathematical conditions for improved
diagnosis using iterative bootstrapping
Applied iterative bootstrapping in novel ways (TMR,
shuffled TPGs, TPGs w/o i/o faults) to develop a Mixed
BISTer M-BIST sans fault-free assumptions
Achieved our aim of accurate PLB and interconnect
diagnosis
Future Work: Built-in controller for diagnosis and
reconfiguration
THANK YOU
Built-In Self-Test in FPGAs—On-Line & Off-Line
•• InTwo
column left spare for ROTE; one for
each session diff. PLBs act as CUTs,
ROTE (ROving TEster)
fault reconfiguration
TPG and ORA.
• ROTE roves across the FPGA
BISTer:
C
T
C
O
O
C
CIRCUIT
CIRCUIT
SPARE COLUMN
CIRCUIT
T
C
TPG - Test Pattern Generator
ORA - Output Response
Analyser
CUT - Cells Under Test
WUT - Wires Under Test
TPG
CUT
WUT
CUT
WUT
ORA
Pass / fail
Mixed-BIST: Interconnect BIST Stages (contd)
Global testing
n2 n1 l2
Detailed testing—Divide-&-Conquer
n2a
l1
l2a
O
O
O
Switch stuck-closed
O
A
n2b
l2b
TPG
O
Suspect interconnect
Fault-free interconnect
ORA
M-BISTer (Mixed-BISTer):
Interconnect global testing: detect {tracks} using TMR
o/p = T-FF -> {ff tracks}
TMR’ed
non-T-FF -> {suspect tracks}
PLB bootstrapping: detect {ORAs, TPGs} using T-FF set
Interconnect detailed testing: diagnose {interconnects of non-T-FF}
using ORA-FF set.
o/p = I-FF -> {ff interconnects} non-I-FF -> {faulty interconnects}
PLB Fault detection: detect {suspect PLBs} using ORA-FF set and I-FF set.
o/p = suspect set = {PLBs suspected of being faulty}
PLB adaptive fault diagnosis: diagnose {faulty PLBs among suspect set}
using ORA-FF set and I-FF set.
o/p = PLB-FF -> {ff PLBs} non-PLB-FF -> {faulty PLBs}
Non TMR’ed
o/p = ORA-FF -> {ff ORA + TPG PLBs}