Memory: Page Table Structure
CSSE 332
Operating Systems
Rose-Hulman Institute of Technology
Memory management unit
•Translates Virtual Addresses
page tables
translation lookaside buffer (TLB)
•Page tables
One for kernel addresses
one or more for user space processes
•Page Table Entry (PTE) for user space
processes
Typically 32 bits
page frame, protection, valid, modified, referenced
Address translation
A logical address
Virtual page number + offset
•Finds PTE for virtual page number
•Extract frame number and append offset
•Fail (MMU raises an exception - page fault):
bounds error - outside address range
validation error - non-resident page
protection error - not permitted access
Imagine you have a computer that has 32 bit
logical addresses. Given that a page is 4KB (212
bytes) …
a) what is the minimum size of a page table entry,
assuming physical addresses in this system are 32
bits?
b) How big (in total) must the page table for each
process be, assuming each page table entry was 4
bytes?
Structure of the page table
•Hierarchical Paging
•Inverted Page Tables
•Inverted Page Tables with Hashing
Hierarchical page tables
•Break up the logical address space into
multiple page tables
•A simple technique is a two-level page table
Two-level page-table scheme
Two-level paging example
•A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
•Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
page number
pi
p2
12
10
page offset
d
10
where pi is an index into the outer page table, and p2 is the
displacement within the page of the outer page table
Two-level page table example (2)
Consider a process as described here:
•Logical address space is 4-GB (232 bytes)
•Size of a page is 4KB (212 bytes)
•There are ___ pages in the process.
This implies we need ____ page table entries in the
process page table.
•If each page table entry occupies 4-bytes, then we need a
______ byte large page table
The page table will occupy __________ pages.
•Root table will consist of ____ entries
one for each page that holds part of the process page
table
•Root table will occupy ____ bytes
4KB of space will be kept in main memory permanently
•A page access could require two disk accesses
Two-level page table example (3)
Consider a process as described here:
•Logical address space is 4-GB (232)
•Size of a page is 4KB (212 bytes)
•There are 220 pages in the process. (232/212)
This implies we need 220 page table entries in the process
page table, one entry per page.
•If each page table entry occupies 4-bytes, then we need a 222
byte (4MB) large page table.
The page table will occupy 222/212 i.e. 210 pages.
•Root table will consist of 210 entries
one for each page that holds a part of the process page
table
•Root table will occupy 212 bytes
4KB of space will be kept in main memory permanently
•A page access could require two disk accesses
Always in
main
memory
Brought into
main memory
as needed
Inverted page table
•The page table can get very large
•An inverted page table is another solution
•An inverted page table has an entry for every frame in
main memory and hence is of a fixed size
This is why it is called an inverted page table
Also contains info to identify process
•A hash function is used to map the page number (and
process ID) to the frame number
•A PTE has
a page number, process id, valid bit, modify bit,
chain pointer
Inverted page table
Virtual Address
Page #
Physical Address
Frame #
Offset
Inverted
Page Table
Offset
Page Frame
Frame #
<PID, Page #>
Search
V M PID,Page #
matches Page #
and PID
Program
Paging Hardware
Memory
Inverted page table with hashing
Virtual Address
Page #
Hash
<PID, Page #>
Physical Address
Frame #
Offset
Offset
Hash Table
Inverted
Page Table
Page Frame
Frame #
Synonym Chain
Search
Program
V M PID,Page #
matches Page # and
PID
Paging Hardware
Memory
Hashing techniques
Hashing function: X mod 8
(b) Chained rehashing
Memory management concerns
• Problem:
• Page tables require at least 2 memory access per instruction
• One to fetch the page table entry
• One to fetch the data
• Solution: Translation Lookaside Buffer (TLB)
• A high-speed HW associative cache set up for page table entries
• Cache the address translations themselves
Associative cache
Direct page lookup
Associative page lookup
Typical TLB use
Effective access time with TLB
• In tlb = 10ns (TLB) + 100ns (data)
• not in TLB: 10ns (TLB) + 100 (PT) + 100ns (data)
• Effective access time = 110ns (.90) + (1-.90) * 210ns = 120ns
Typical TLB parameters
Block Size
4 to 8 bytes (1 page table
entry)
Hit Time
2.5 to 5 nsec (1 clock cycle)
Miss Penalty
50 to 150 nsec
TLB Size
32 bytes to 8 KB
Desired Hit Rate 98% to 99.9%