EFFICIENT MINIMUM GROUP DELAY BLOCK PROCESSING APPROACH TO
FRACTIONAL SAMPLE RATE CONVERSION
Alexandra Groth and Heinz G. G öckler
Digital Signal Processing Group, Ruhr-Universität Bochum,
Universitätsstr. 150, D-44780 Bochum, Germany
ABSTRACT
The derivation of block-processing structures for fractional
sample rate conversion (FSRC) is revisited. In the past, several time- or frequency-domain approaches [1-6] have been
proposed. However, the resulting structures differ concerning their group delay and, as a consequence thereof, in the
arrangement of coefficients. In this paper it is shown that
a minimum extra delay of z (ML L M +1) is sufficient to
ensure causality. This outcome is demonstrated both in frequency- and time-domain.
1. INTRODUCTION
In digital systems rational sample rate conversion performed
by a fractional sample rate converter (FSRC) is one of the
basic tasks. The system theoretic approach is a cascade connection of an L-fold upsampler, a filter H (z ) and an M -fold
downsampler (Fig.1), where H (z ) combines anti-imaging
and anti-aliasing filtering. As a consequence, all filter operations have to be performed at the highest rate, which is
related to the system input rate f i by Lfi .
Recently, various derivations of block processing realizations have been published [1-6]. As a result, efficient structures (Fig. 5) are obtained, where filtering is completely
performed at a fixed subnyquist rate f i =M . As a consequence, the computational expenditure is reduced by a factor LM . While the computational load of all block processing structures is identical, their group delay is always
different. This is a result of the additional delay z r which
is introduced for eliminating anti-delays from the derived
structures (r = ML L [1,2]; r = max 8m [m L] with
= l M m L, 2 f0; : : : ; M 1g or r = max8l [l M ]
with = m L l M , 2 f0; : : : ; L 1g [3,4,5]; r =
min[(ML
d ML+1 eL); (ML d LM+1 eM )] [6]).
In contrast to previous publications [1-6], the aim of this
contribution is to deduce a block processing structure where
the extra delay is kept to a minimum. For the sake of completeness a time as well as a frequency domain derivation
is given. In section 2, the subnyquist system is deduced by
exploiting the noble identities [7]. The same structure is
obtained by a type 1 and 3 time domain polyphase decomposition [7, pp. 120-122] of the FSRC (Section 3).
2. FREQUENCY-DOMAIN DECOMPOSITION
Comparing Fig. 1 and 5 we observe that a block processing
structure is obtained by reversing the order of the L-fold upand the M -fold downsampler. This can be achieved by exploiting the noble identities [7] provided that z r H (z ) has
previously been transformed into a system consisting only
of L-, LM - and M -fold delays. Note that the main goal
in this transformation procedure is the minimization of the
additional delay z r .
Shifting
X(zi )
z -r
H(z)
M
Y (z o )
Shifting
Figure 1: Fractional sample rate converter (FSRC) with an
additional delay z r (r 2 N 0 ).
Without any loss of generality, we restrict our considerations to FSRCs with coprime L and M because every FSRC
with arbitrary L and M can be reduced to a system with coprime factors .
Step 1: Polyphase Decomposition of H (z )
In the derivation process we start with an LM -branch polyphase decomposition of the FSRC filter according to
z r H (z )
This work was supported by Deutsche Forschungsgemeinschaft under
contract GO 849/1-1.
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0-7803-6685-9/01/$10.00©2001 IEEE
L
=
LM
X1
=0
z r H (z LM ) :
(1)
As a result, we obtain a system only consisting of filters
H (z LM ) with LM -fold delays (Fig. 2). However, branch
delays z r which are not L- or M -fold multiples of the
unit delay still exist.
z -r
L
H 0(z LM)
z -r-l
z -r-LM+1
H (z )
into
LM
L
(2)
+1
unknown variables
lLM 1 r]T
(3)
z -ml L
)
z
-gLM-1 LM
M
B
B
B
@
0
0
..
.
..
.
0
0
L 0
z -lLM-1 M
HLM-1 (z LM)
..
.
0
..
.
0
1
0
..
.
M
..
.
10
B
1 C
CB
1
and l
=
modulo M and 0 x
=
;
(6)
bxc < 1.
0
0
1
0
C B
C B
CB . C = B
A @ .. A @
r
1
0
C
C
C
A
1
..
.
LM
< r min .
rmin is a solution of Eqs. (4,5).
L + M
=
ML L M ;
(7)
which is independent of all others, has to be solvable. However, this diophantine equation
au + bv = c with a; b; c 2 Z
(8)
is solvable if and only if the greatest common divisor d of
a; b) divides c as well. In this case, the set of solutions is
given by [8]
(
u; v) =
; ) =
In order to derive r min the system of equations (Eq.(2)) is
modified by combining m and g according to
L M
M
Proof of Theorem 1: Suppose the statement is false. To
this end, let = ML L M r 2 [0; LM 1] with
r 2 [0; rmin 1], then the -th row of Eq. (4)
(
Figure 3: Decomposition of branch delays according to
z r = z mL z gLM z l M .
0
(5)
u0 + tb v0 ta
;
d
d
t
2Z
(9)
with (u0 ; v0 ) being one known solution. Thus we obtain
z -ll M
z -g lLM Hl (z LM)
z -mLM-1 L
j k
Theorem 1: No solution of Eqs. (4,5) exists for r
(
z -l0 M
LM
H0 (z
; r0
1
1. Hence, the solution of the original
Eq. (2) can be deduced by
Theorem 2:
are non-negative integers, where g 2 f0; 1g. The additional constraints m 2 f0; : : : ; M 1g and l 2 f0; : : : ; L
1g are necessary for the final structural reduction to allow
blocking and unblocking as shown in Fig. 5.
z -g0 LM
L
Eqs. (4,5) represent a system of linear diophantine equations which can be solved by number theory [8]. As a result,
we obtain rmin = ML L M + 1 out of the multitude
of solutions. In order to guarantee that r min is the minimum
solution the following two theorems have to be proved:
Step 2: Decomposition of the branch delays z r The next intermediate step is the partitioning of the branch
delays z r into L-, (LM )- and M -fold delays subject to
r being minimum (Fig. 3):
z r = z mLz g LM z lM ; 8 = 0; : : : ; LM 1:
z -m0 L
0
8 = 0; : : : ; LM
where ( )M
Figure 2: Polyphase decomposition of
polyphase components .
m0 g0 l0 m1 : : :
;
1
m = ( )M ; g =
HLM-1(z LM)
[
2M
0
M
Hl (z LM)
As a matter of course the 3LM
with the constraints
(
1+
tM; L
1
tL) t 2 Z
;
(10)
where = 1 and = L 1 is one particular solution.
However, note that in the whole set of solutions none of
them is within the given bounds (Eq. (5)).
Proof of Theorem 2: In the case of r min Eq. (4) consists
of LM independent linear diophantine equations with the
solutions
; ) = (u0 + tM; v0
(
tL) t 2 Z
:
(11)
As a consequence thereof, each equation has a solution within the bounds 0 L 1. Thus, each does not
exceed the interval:
smallest value 8
L
(
1
(4)
II-190
rmin =ML L M + 1
) 1 + L1 = 0
(12)
M + L
1)
highest value 8
rmin + LM 1 = 2ML L M
) 2M 1 M
2M 1
(13)
L
L
zi-m0
zi-ml
zi-mLM-1
M
zs-g0 H0 (zs )
L
M
zs-gl Hl (zs )
L
M
z s-gLM-1 HLM-1(zs )
L
M
MIMO
L
zo-1
zo-1
LTI
System
M
z-1
i
zo-1
L
zo-1
S(z s )
M
L
1-to-M blocking
L-to-1 unblocking
Figure 5: Desired block processing structure [1-6].
related to the input signal x(n) by [7]
y (k ) =
r
bk MX
L Lc
n=
1
x(n)h(kM
nL r) ;
(14)
with r being the unknown additional delay. Since the final
block processing structure comprises an input decimator delay chain system (which decomposes the input signal x(n)
into polyphase components
zo-l l
x(n) =
zo-lLM-1
Step 4: Rearrangement of Branches
Finally a pooling of branches with the same input z i m or
output delay z o l is required in order to minimize the total number of data storage in the system. As a consequence
thereof, we obtain the desired block processing structure requiring only one input decimator- and one output interpolator-delay chain circuit (Fig. 5).
M
X1 In the previous section a rigorous and straightforward derivation is given, where ML L M + 1 extra delays are introduced by the decomposition of the branch delays z r .
In this section the above result is obtained by a time-domain
polyphase decomposition confirming that at least ML L
M + 1 extra delays are required to ensure system causality.
1 is
x(jM
;
m);
for jM m = n
otherwise
0
m=0
(15)
and reduces the sampling rate by deleting the zeros) and an
output interpolator delay chain circuit which interleaves the
polyphase components of the output signal y (k ) according
to
LX1 l=0
y(iL + l);
0;
for iL + l = k
otherwise
=
y(k)
(16)
the substitutions k = iL + l with i 2 Z, l 2 f0; :::; L 1g
and n = jM m with j 2 Z, m 2 f0; :::; M 1g are
introduced into Eq. (14). As a result, we obtain
y[iL + l]
3. TIME-DOMAIN POLYPHASE
DECOMPOSITION
y(k) of the system depicted in Fig.
L
z-1
i
zo-l0
Figure 4: Interchange of up- and downsampler by exploiting
the noble identities (z i = z L , zo = z M and zs = z LM ) .
The output signal
L´M
z-1
i
Hence, it is proven that at least one solution ( ; ) for
each equation exists within the given bounds. As a consequence thereof the overall system of equations is solvable
for rmin .
Step 3: Interchanging of up- and downsamplers
By applying the noble identities [7] the following building
blocks can be interchanged: i) upsampler and subsequent
L-fold delay, ii) M -fold delay and subsequent downsampler and iii) up- and downsampler. The resulting structure
is depicted in Fig. 4.
M
zi-1
=
M
X1
m
r
i+b Ll +X
M LM c
x[jM m] 1
h[(i j )LM + lM + mL r] :
m=0
j=
cLM
The substitution = b LM
mL r leads to
y[iL + l] =
M
X1
m=0
+ ( )LM
m
r
i+b Ll +X
M LM c
j=
1
(17)
with = lM
x[jM
m]
+
(18)
mL r LM + (lM + mL r) :
h i j + lM +LM
LM
II-191
with ( stands for convolution)
By defining the polyphase components of type 1 [7]
yl(p1) [i]
h(p1) [ ]
=
=
y[iL + l]
h[LM + ]
(19)
(20)
h
and type 3
x(mp3) [j ]
=
x[jM
m] ;
(21)
Eq. (18) can compactly be rewritten as
yl
p
( 1)
i
[ ]=
m
r
i+b Ll +X
M LM c
M
X1
j
lM +mL r :
+
LM
1. The original overall system has to be causal [1], i.e.
nL r) j(k ML )<(n+ Lr ) = 0
lM +mL r +
LM
=0
i<j
(24)
8i; j . Due to block processing the sampling instants
(, calculation of output signal) are iL( M
L Ti ). Therefore only input signals up to jMT i iL( M
L Ti ) can
be considered when calculating the output signal. As
a consequence, the impulse response has to be zero
for all times jMTi > iMTi , i.e. for j > i.
Provided that the original FSRC is causal (condition 1), conditions 2 can only be satisfied, if for Eq. (22)
i j+
holds or
lM + mL
LM
r lM + mL r
LM
i<j
<0
m=0
p
lM mL ML+L+M
( 1)
(
+
1)LM
+L+M
i + lM +mL ML
LM
1
Comparing the derived algorithm according to Eq. (28) with
the structure depicted in Fig. 5, one can easily prove the
identity of both.
8m; l
0 8m; l
A novel systematic and rigorous derivation of a block-processing structure representing a fractional sample rate converter has been given. Conditions for minimum extra delay which is necessary to guarantee causality are, for the
first time, derived and proven in both time- and frequencydomain. As a consequence, a block processing approach to
FSRC with absolutely minimum group delay is obtained.
(23)
2. All subsystems have to be causal, i.e.
x(mp3) [i]
(22)
To guarantee causality, the following requirements have to
be met:
h((plM1)+mL r)LM i j
M
X1
4. CONCLUSION
x(mp3) [j ]
m=0
j= 1
(p1)
h(lM +mL r)LM i
h(kM
yl(p1) [i] =
(25)
5. REFERENCES
[1] H.W. Schüßler, Digitale Signalverarbeitung 1, Analyse diskreter Signale und Systeme, Springer Verlag,
Berlin, 1994.
[2] T. Miyawaki, C.W. Barnes, Multirate Recursive Digital Filters-A General Approach and Block Structure,
IEEE Trans. on Acoustics, Speech, and Signal Proc.,
Vol. ASSP-31, No. 5, Oct. 1983, pp. 1148-1154.
[3] C.C. Hsiao, Polyphase Filter Matrix for Rational
Sampling Rate Conversions, IEEE Int. Conf. Acoustics, Speech, Signal Processing ICASSP ’87, Dallas,
1987, pp. 2173-2176.
[4] P.P. Vaidyanathan, Multirate Digital Filters, Filter
Banks, Polyphase Networks, and Applications: A Tutorial, Proc. of IEEE, Vol. 78, No. 1, Jan. 1990, pp.
56-93.
(26)
[5] G. Bi, Minimisation of Delay Requirements for Rational Sampling Rate Alternating Systems, ICASSP
’91, Toronto, Ont., Canada, Vol. 3, May 1991, pp.
1817-1820.
(27)
[6] H.G. Göckler, G. Evangelista, A. Groth, Minimal
Polyphase Implementation of Fractional Sample Rate
Conversion, Signal Processing, Vol. 81, No. 4, 2001.
resp. Hence, this leads to
r
2 f[ML L M + 1]; :::; 1g :
In order to obtain the smallest additional delay, we choose
r = rmin = ML L M + 1. Thus, the block processing
structure can be described in the time domain by
y(k) =
LX1 l=0
yl(p1) (i);
0;
for iL + l = k
otherwise
(28)
[7] P.P. Vaidyanathan, Multirate Systems and Filter
Banks, Prentice Hall Signal Processing Series, 1993.
[8] P. Bundschuh, Einf ührung in die Zahlentheorie und
Algebra, Springer Verlag, Berlin, 1998.
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