Final Exam – Part 1
ECE 3561
(70 points) In this problem you are to design an 8-bit comparator that compares 2 8-bit words, A
and B. The outputs are 3 signals (1-bit each), oAgtB, oAeqB, and oAltB. So the units can be
chained to create a larger comparator there are 3 single bit inputs, AgtB, AeqB, and AltB.
A
B
8
8
oAgtB
oAeqB
oAltB
AgtB
AeqB
AltB
It is easiest to create this unit by creating a 1-bit comparator unit with
the inputs Ai, Bi, AgtB, AeqB, and AltB. These can then be chained together to create an 8-bit
unit.
Ai Bi
oAgtB
oAeqB
oAltB
AgtB
AeqB
AltB
Create a report that has the following sections.
1) (5 points) Statement of the specification for the unit to be designed.
2) (15 points) VHDL code for the 1-bit comparator.
3) (5 points) Screen shot of the Modelsim window showing successful compilation of the
unit. It should look like the following.
ECE 3561
Final Exam – Part 1
4) (15 points) VHDL code for the structural 8-bit comparator formed from by using 8 of the
1-bit units.
5) (5 points) Screen shot of the Modelsim window showing successful compilation of the
unit.
6) (20 points) Now enter the design into Quartis and synthesize it. Use screen capture (as
done above using ctl-alt-printScreen and then pasting into the word document) to capture
the information showing that the unit successfully synthesized. The report should include
the compilation statistics as to how many CLBs the design took, and screen shots
showing the architecture generated for the 8-bit unit. Then descend the hierarchy and
show the architecture generated for the 1-bit unit.
7) (5 points) A summary statement that summarizes the HDL design and then the synthesis
in Quartis highlighting the significant points of the design. For the unit to operate
correctly what must each of the inputs AgtB, AeqB, and AltB be set to?