Moore’s Law – the Z dimension
Sergey Savastiouk, Ph.D.
[email protected]
April 12, 2001
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Presentation Overview

Introduction: The next dimension is the Z dimension

Step 1: Vertical miniaturization – thinning
– Thinner is better
– Thinning and handling problems and solutions

Step 2: Vertical integration – stacking
– Thru-Silicon vias
– 3D stacking for system-in-a-chip (SIP)

Conclusion: 3D Wafer Level Packaging
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Moore’s Law – the X-Y dimensions.
The number of components on a surface of a chip would double every 18 – 24 months.
Moore’s Law - the Z dimension
The number of components in 3D space would double every 18 – 24 months.
Si
Si
Si
Si
Si
Si
Si
?
Si
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Packaging trends
1985
1990
1995
STACK
TSOP
SOP
TCP
STACK MEMORY MODULE
BARECHIP
QFP
PACKAGE
2000
SYSTEM ON MODULE
MCM
TQFP
DIP
BGA
PGA
CSP
SYSTEM ON SILICON
LITHOGRAPHY
DESIGN
RULE
PIN COUNT
0.5um
0.8um
1M
4M
200
0.25um
0.35um
16M
300
64M
1000
0.18um
256M
2000
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Package and Chip Thickness
7000
DIP
6000
5000
PDIP
Package
Thickness
Bare Die
Thickness
4000
3000
TQFP
BGA
2000
CSP
1000
STACK
MODULES
0
1981 1986 1992 1996 1999 2002 2006 2012
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Wafer and Chip Thickness
900
800
700
600
DIP
500
PDIP
400
300
TQFP
BGA
TSSOP
200
STACK
MODULES
CSP
100
0
1960
1970
1980
1990
2000
2010
2020
Year of Significant Production
Wafer Diameter, mm
Wafer Thickness, um
Chip Thickness, um
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• Step 1: Vertical miniaturization – thinning
Thinner is better
Why to thin?
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Thinner is better

WHY to thin ?
Better packaging density
 More flexible
 More reliable
 Better thermal resistance
 Better yields

50 mm wafer.
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Thinning for smaller space: Why to thin?
Si
H1
Si
H2
Reduction of thickness by half provides
50% reduction in height and 30% in footprint of packaging
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Thinning for flexibility: Why to thin ?
Hitachi

<100 micron thickness for improved reliability,
requires damage-free silicon
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Numerical results for reliability: Why to thin ?
Thick chip:
u = 700 mm,
b = 1000 mm
Thin chip:
u = 50 mm,
b = 200 mm
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Improved Power Dissipation: Why to thin?
Thermal Resistance vs. Thickness
Thermal Resistance (Deg.C/Watt)
0.05
0.045
0.04
0.035
0.03
Chip
Adhesive
Chip+Adhesive
0.025
0.02
0.015
0.01
0.005
0
50
100
200
Chip Thickness (microns)
300
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• Step 1: Vertical miniaturization – thinning
Thinning and handling problems
and solutions
How to thin?
How to handle thinned wafers?
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Thinning alternatives
Grinding (leaves damage)
 Polishing (leaves some damage)
 Wet etching (removes damage, but wet)
 Dry etching (removes damage)

Damage
Silicon
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Atmospheric Downstream Plasma: How to thin?
Si WAFER
SiF4
CO2
CO
C + 4F
Argon
CF4
•No induced electrical damage
•No vacuum pumps – excellent process control
•Etch rate suitable for mass production
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Edge damage yield problems: How to handle?

Damaged edges cause wafers to break
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NoTouch™ wafer holding: How to thin?
Holding Gas
NoTouch
Holder
Wafer Back Side
Atmospheric
Downstream
Plasma
•Maintains planarity of flexible wafers
•No contact with bumps
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Damage-free wafer surface: How to thin ?
Damage
Silicon
No damage
Silicon
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Damage free edges: How to thin?
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Thinning alternatives: How to thin?
After grinding or polishing
After wet spin etching
Old
technologies
After ADP etching
New ADP
technology
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Die strength etching vs. grind & CMP: How to
thin?
Front tensile strength Weibull plot
160um thick die (35 mm squared)
Survival probability(%)
100
Grind & cmp /Front side
Plasma 10um /FS
Plasma 20um /FS
10
1
0
200
400
600
800
1000
1200
Tensile strength (N/mm2)
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Wafer warp improvement
Post-ADP Warp
Post-grind Warp
16
14
Warpage (mils)
12
10
8
6
4
2
0
8
10
12
14
16
18
20
Final Wafer Thickness (mils)
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Damage Free Dicing (in development)
Step 1. Grind
Step 2. Controlled
depth dicing
Individual dice
Step 3. Apply top
side tape
Step 4. Etch the
backside to singulate
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DBG
vs.
Sawed die showing chipping
Chip Shifts and Cracks
Damage Free Dicing
40 micron thin ADP etched dice,
rounded and smoothed
No Chip Shifts and Cracks
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Damage Free Dicing
Die top
SEM pictures
of the edges
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• Step 2: Vertical integration – stacking
How to thin and to bump on a
backside in one step?
How to stack?
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Integration: SOC vs. SOB ,SIP ?
SIP
SOB
SOC
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ADP Via Etch
(continued)
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ADP thinning of via (continued)
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Thru-Silicon via
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Thru-Silicon via results
Back Side of a wafer with contact pad
Silicon
Metal
SiO2
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Thru-Silicon via results
Back side of a wafer with contact pads
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Tru-CSP™ for front side up : project
Direct Chip Attach
Active Circuitry
Front Side Passivation
Substrate Or PWB
Solder Paste Or Other
Joining Material
Exposed Through
Hole Contact
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Tru-CSP™ for opto-electronics: project
Opto-Electronic Devices
Optical Signals Can Be Transmitted And
Received From Either Surface
Optically Transparent Layer Or Optical Waveguide
Optical Waveguide Or Other Silicon Device
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Tru-CSP™ with passive interposer : project
Passive Interposer
IC Connected To Passive Interposer Using Any
Convienient Joining Technique (e.g. flip chip, ACA, etc.)
Surface Of Interposer Contains Elements Like Resistors,
Capacitors, Inductors, Networks, Power And Ground
Planes And Other Performance Enhancing Functions
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Tru-CSP™ face-to-face : project
Active Devices Joined
Face-To-Face
Top Wafer/Device Can Be With Or Without
Thru-SiliconConnections
Active Circuitry
Wafers/Devices Joined Using Any Suitable Joining
Technique (i.e. Flip Chip, Anisotropic et al.)
While Perimeter Contacts Are Shown, Thru-Silicon Connections Can Also Be Area Array
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Tru- 3D Stacking : project
3D Stacking
Additional Wafers Can Be Added To The Stack
An Active Wafer Is Joined To A Passive Interposer Or Other
Active Wafer Using Any Convienent Joining Method. The Top
Wafer Is Then Thinned To Expose The Through Hole
Contacts And The Next Wafer Added.
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Conclusion: History of Company

1997, $8m raised, ADP prototyping

1998, Ultra-thin handling prototyping

1999, $10m raised, Product development

2000, System sales and Thru-Silicon dev-t

2001, $18m raised, – Thru-Silicon dev-t
hiring process engineers: [email protected]
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Conclusion: Overall Summary
Thinning
by ADP and NoTouch handling:
– enables low cost damage free thinning
– enables low cost damage free dicing
Thinning
by ADP with Thru-Silicon vias:
– enables the new generation of low cost 3D stacking
methods of chips and wafers for System-In-a-Package
– brings front-end technologies to back-end applications
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