Progress report on the
LPSC-Grenoble
contribution in microelectronics (ADC + DAC)
J-Y. Hostachy, J. Bouvier, D. Dzahini, L. GalinMartel, E. Lagorio, F-E. Rarbi, O. Rossetto, C.
Vescovi
1
Fast Digitizer for CALICE
preamp
preamp
preamp
Shaper_1
Memory
Shaper_10
Memory
Shaper_1
Memory
Shaper_10
Memory
Shaper_1
Memory
Shaper_10
Memory
MUX
32/641
J-Y. Hostachy et al., LPSC-Grenoble
12 bits
Fast
ADC
2
Why a high speed ADC ?
 Multiplex 32/64 to 1 ADC
 High speed converter:
 Read all channels faster
 More “IDLE mode” time => Saving power
 digital noise source from one ADC
Acquisition
A/D conv.
DAQ
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
A/D
conv.
199ms (99%)
99% idle cycle
1% duty cycle
Acquisition
IDLE MODE
DAQ
IDLE MODE
Extra power
saving
J-Y. Hostachy et al., LPSC-Grenoble
3
25 MHz, 12 bits, 2Vpp Pipeline ADC
Bias stage
Full 1.5 bit
per stage
Digital correction
1.5 bit stage
4
Tests of the pipeline ADC
- Power supply could be reduced =>
Extra Power Saved
σ < 0.6 LSB
- Wide noise margin
2V
INL: < 4 LSB
DNL: < 1 LSB
5
Average Power Pulsing Budget
Memory depth= 16
# of channel = 64
With Power pulsing
PMUX= 7 mW
TTC (Total Time conversion) = 40ns x 64
x 16
Tc = 40 ns
PADC= 37 mW
= 41µs
MUX + ADC Power Consumption per channel = ((PADC+PMUX) x TTC)/200ms/64ch
141nW/channel
6
A multi bit
2.5 bits
1st stage
ADC
1.5 bit stage
Bias stage
3 bit Flash
Vin
+
+
residue
x4
-
ADC
Digital correction
S/H
DEM
DAC
2.5 bit stage
MDAC
2.5 bits
Back -end ADC
Front -end stage
Vin
stage 1
2.5 bits
…
stage 2
1.5 bit
8
stage 10
1.5 bit
FLASH
3 bits
data delay + digital correction
12 bits
7
Dynamic Element Matching (DEM)
Dynamic Element Matching effect (simulation estimate)
Distortion reduced => Improvement of INL
Without DEM => INL = 4 LSB
SFDR=60dB
With DEM => INL = 0.4 LSB
SFDR=80dB
J-Y. Hostachy et al., LPSC-Grenoble
8
16 bit Sigma Delta DAC
Fine results but an integrated
filter is needed to generate a DC
signal
This is not trivial, this is why we
consider another architecture
“C2C”
6
INL(LSB)
4
INL 1
INL 2
INL 3
INL 4
INL 5
16 bits with INL = +/- 4LSB
2
0
0
10000
20000
30000
40000
50000
60000
70000
-2
-4
9
-6
12 bit 4 MHz DAC for calibration
(Segmented arrays of switched capacitors)
12 bits with INL = +/- 0.4 LSB
This 12 bits is the basis to go forward
to a 14 and 16 bit version.
J-Y. Hostachy et al., LPSC-Grenoble
10