The World Leader in High-Performance Signal Processing Solutions
Direct Digital Synthesis
Theory & Applications
1. Theory (why & how it works)
2. Error Sources
3. Advanced DDS Capabilities
4. Applications Examples
[email protected]
Phase  Time
Fout
TIME
360
PHASE
0
q = 360t*Fout
TIME
1
Discrete Phase  Discrete Time
Fout
TIME
n
2 -1
Fout =
PHASE
0
1
Fclk
Fclk
2n
TIME
2
How do you build this?
n
2 -1
Fout =
PHASE
0
Fclk
2n
TIME
PHASE ACCUMULATOR
n = 24 - 48 BITS
n
n
1
PHASE n
REGISTER
CLOCK
Fclk
3
Changing Frequency
n
2 -1
Fout = M
PHASE
0
Fclk
2n
TIME
PHASE ACCUMULATOR
n = 24 - 48 BITS
n
n
M
DELTA
PHASE
M
REGISTER
M
FREQUENCY CONTROL
M = TUNING WORD
n
PHASE n
REGISTER
CLOCK
Fclk
4
Getting a Sinewave Output
Fout = M
AMPLITUDE
0
Fclk
2n
TIME
PHASE ACCUMULATOR
n = 24 - 48 BITS
n
n
M
DELTA
PHASE
REGISTER
M
FREQUENCY CONTROL
M = TUNING WORD
n
PHASE n
REGISTER
p
PHASE-TO
AMPLITUDE
CONVERTER
CLOCK
Fclk
5
Signal Flow Through the DDS Architecture
M = JUMP SIZE
Fo = M
Fclk
2n
REFERENCE
CLOCK
Fclk
fo =
DDS CIRCUITRY (NCO)
n
M
PHASE
ACCUMULATOR
(n-BITS)
PHASE-TO-AMPLITUDE
CONVERTER
N
DAC
M • fc
2n
TO
FILTER
TUNING WORD SPECIFIES
OUTPUT FREQUENCY AS A
FRACTION OF REFERENCE
CLOCK FREQUENCY
DIGITAL DOMAIN
ANALOG
6
Another Way to Look at DDS
vector data
raw DDS-DAC output
filtered output
compared output
31
29
…
6-bit
phase
wheel
4
3
2
1
0
63
…
4
2
0
5-bit
amplitude
resolution
7
The World Leader in High-Performance Signal Processing Solutions
Direct Digital Synthesis
Theory & Applications
1. Theory (why & how it works)
2. Error Sources
3. Advanced DDS Capabilities
4. Applications Examples
[email protected]
Errors in a DDS System
PHASE ACCUMULATOR
n = 24 - 48 BITS
n
M
DELTA
PHASE
REGISTER
M
FREQUENCY CONTROL
M = TUNING WORD
n
n
n
PHASE n
REGISTER
p
PHASE-TO
AMPLITUDE
CONVERTER
CLOCK
PHASE
TRUNCATION
12-19 BITS
N-BITS
(10-14)
AMPLITUDE
QUANTIZATION
F clk
DAC
SYSTEM CLOCK
DAC ERRORS
F out
Fout = M
Fclk
2n
9
Amplitude Errors
 Quantized waveform ≠ Sinewave
 Therefore there will be spectral components
 6.02N + 1.76 quantization noise is only valid when clock
and data are uncorrelated. NOT THE CASE for a DDS!
 DAC non-linearities
 INL and DNL spurs will alias
 Harmonics from the analog output stage will NOT alias
10
Aliased Distortion Terms
Distortion in an analog system
Freq
Distortion in an sampled system
Fs
2Fs
Freq
All the distortion terms show up in the passband
11
Effects of Choosing an Odd Value For M
n
2 -1
PHASE
M=4
0
n
2 -1
TIME
30
31
28
29
30
27
M=5
PHASE
0
TIME
12
Effect Sampling Clock / Output Frequency
Ratio on SFDR for Ideal 12-bit DAC
(A) FOUT = 2.0000 MHz, fS = 80.0000 MHz
(B) FOUT = 2.0117 MHz, fS = 80.0000 MHz
SFDR = 77dBc
Ratio = 80/2 = 40
FFT SIZE
THEORETICAL 12-BIT SNR
FFT PROCESS GAIN
FFT NOISE FLOOR
SFDR = 94dBc
Ratio = 80/2.0117 = 103/4096
= 8192
= 74dB
= 36dB = 10log(8192/2)
= 110dBFS
13
Phase Truncation Errors
 Green points (outer circle) show n=8
phase accumulator
 256 phase steps
 M=6 in this illustration
 Red points (inner circle) show p=5
 32 steps passed on the phaseamplitude converter
 3 points get truncated, but the 1st and
4th do not
 As the phase moves around the
circle, the error becomes periodic
 Phase error = Amplitude error
 Due to phase-amplitude converter
 Periodic phase error = periodic
amplitude error = spectral
component
14
Phase Truncation Error (Time Domain)
 Not only is the error periodic, but it also has a ramp shape
 Therefore we expect the spectral components fall at a 1/m
rate (m = harmonic number)
15
Phase Truncation Error (Frequency Domain)
 However, since this is a phenomenon in the digital domain,
these spurs will alias.
 The largest spur is approximately -6.02p dBc
 (e.g., -72 dBc for p=12)
16
The World Leader in High-Performance Signal Processing Solutions
Direct Digital Synthesis
Theory & Applications
1. Theory (why & how it works)
2. Error Sources
3. Advanced DDS Capabilities
4. Applications Examples
[email protected]
Additional DDS Capabilities
 Add Frequency Register
 Sweep
 Chirp
 RAM profiles
 Amplitude control
 IQ modulation
 Multi-DDS
 For arrays
 Phase offset/compensation
 Spurkiller
18
Frequency Control
PHASE ACCUMULATOR
n = 24 - 48 BITS
n
PREPROGRAMMED
M
FREQUENCY
CONTROL
or RAM
n
DELTA
PHASE
REGISTER
M
FREQUENCY CONTROL
M = TUNING WORD
n
PHASE n
REGISTER
p
PHASE-TO
AMPLITUDE
CONVERTER
CLOCK
Fclk
FREQUENCY
TIME
19
Amplitude Control
PHASE ACCUMULATOR
n
n
M
PHASE n
REGISTER
p
PHASE-TO
AMPLITUDE
CONVERTER
DAC
CLOCK
Fclk
AMPLITUDE
REGISTER
20
IQ Modulation
 The DDS is the LO for the Quadrature Modulator
 Everything is in the Digital Domain and can be made as
perfect as necessary by adding more bits
 Upsampling gives the DDS room to move the signal around
21
Multiple DDS
 Precise phase control allows use in beam forming systems
 Each DDS starts up in its own phase
 Phase offsets compensate for phase mismatch in analog
reconstruction filters
22
SpurKiller Technology
 Use an auxiliary DDS channel to add in a signal at the same frequency
and amplitude as the spur, but 180° out of phase with the highest spur…
DDS Channel
for spur reduction
Phase
Offset
Frequency
Accumulator
S
S
DAC
COS(X)
FTW
16
Register
10
14
32
DDS Channel
for phase
modulation
Register
AD9911 DDS
core
DDS Channel
for amplitude
modulation
Register
23
AD9911 SpurKiller 500 MHz DDS
It’s all in
the Digital
Domain!
24
The Results of Using SpurKiller Technology
on a DDS Output Spur
BEFORE
500 kHz / DIVISION
AFTER
500 kHz / DIVISION
OUTPUT FREQUENCY = 166 MHz
Fclk = 500 MSPS
25
The World Leader in High-Performance Signal Processing Solutions
Direct Digital Synthesis
Theory & Applications
1. Theory (why & how it works)
2. Error Sources
3. Advanced DDS Capabilities
4. Applications Examples
[email protected]
Output Circuits
IFS – I
IOUT
ROUT
I
ROUT
IOUT
RSET



IFS 2 - 20mA typical
ROUT > 100k
Output compliance voltage < ±1V for best performance
That is, the output can go below ground!
27
Single Transformer Coupling
MINI-CIRCUITS
ADT1-1WT
1:1
0 TO 20mA
IOUT
LC
FILTER
+0.45dBm
50
CMOS
DAC
VLOAD = ± 0.333V
± 6.67mA
RLOAD
= 50
IOUT
20 TO 0mA
50
Note: The 100 differential primary driving impedance
represents the best compromise between
the effects of transformer impedance mismatch
and DAC SNR performance.
28
Dual Transformer Coupling
VLOAD = ± 0.333V
0 TO 20mA
CMOS
DAC
+0.45dBm
TO
50
LOAD
50 
20 TO 0mA
50 
Mini-Circuits
ADTL1-12
20-1200MHz
Coilcraft
TTWB-1-B
0.13-425MHz
 Transmission Line Transformer in series with outputs to help cancel HD2
 Dual Transformer design helps minimize imbalance caused by mismatched signal coupling from primary to secondary windings.
 RF Transformer from Coilcraft (TTWB-1-B) shows better performance for
IFs at 200-300 MHz
29
Differential DC Coupling Using
a Dual-Supply Op Amp
1000
0 TO 20mA
0V TO +0.5V
500
+5V
–
IOUT
25
CMOS
DAC
AD8055
CFILTER
500
IOUT
20 TO 0mA
+0.5V TO 0V
f3dB =
25
± 1V
+
OR AD8021
–5V
1000
1
2 • 50 • CFILTER
30
Differential DC Coupling Using
a Single-Supply Op Amp
1k
0 TO 20mA
0V TO +0.5V
500
+5V
–
IOUT
25
CMOS
DAC
+2.5V
± 1V
AD8061
CFILTER
+
500
IOUT
+5V
20 TO 0mA
+0.5V TO 0V
f3dB =
2k
25
2k
1
2 • 50 • CFILTER
31
High-Speed Buffered
Differential DAC Outputs
2.49k
0 TO 20mA
0V TO +0.5V
500
+
IOUT
25
CMOS
DAC
VOCM
AD813x
ADA493x
CFILTER
500
IOUT
–
20 TO 0mA
+0.5V TO 0V
f3dB =
25
2.49k
5V p-p
DIFFERENTIAL
OUTPUT
1
2 • 50 • CFILTER
32
Generating a Clock With a DDS
Fsysclock(fc)
DAC out
Filter out
Limiter
Reconstruction
Filter
DDS
Ideal Time
Domain
Response
Clock out
0
t
Ideal
Frequency
Domain
Response
f
t
fc
2fc
f
t
1
f
1
3
5
7
Odd harmonic series
"Real World"
Frequency
Response
f
fc
2fc
f
f
1
3
5
7
 External filtering removes unwanted images
 A squaring circuit converts the signal back to a digital clock
33
Why You Need a Reconstruction Filter
 Fout = 56 MHz, Fclk = 175 MHz
 The MSB does not have a consistent pulse width
 Jitter shows up when unfiltered output is fed directly to a
comparator
34
AN-823 Discusses DDS-based Clocks With
Very Low Phase Noise
CLK = 500 MSPS
Noise - REF
Phase
REF AD9959
CLOCKResidual
= 500MHz,
MULTIPLIER
DISABLED
- 100
Phase Noise (dBc/Hz)
- 110
100.3
MHz
15.1 MHz
75.1
40.1 MHz
40.1
75.1 MHz
15.1
100.3MHz
MHz
- 120
- 130
15.1 MHz
40.1 MHz
75.1 MHz
- 140
100.3 MHz
- 150
- 160
- 170
10
100
1000
10000
100000
1000000
10000000
Phase noise floor
below –150dBc/Hz
Power dissipation <200mW per channel
Frequency Offset (Hz)
35
AD9858 1GSPS DDS
with Phase Detector and RF Mixer
36
PLL General Architecture
Phase/
Frequency
Detector
Loop
Filter
Fref
VCO
RF
÷
N
FRF = N Fref
37
DDS Used as PLL Reference
Phase/
Frequency
Detector
Fref
Loop
Filter
DDS
VCO
RF
÷
N
M
FRF = NM
Fref
2n
38
DDS Used in Fractional-N Loop
Phase/
Frequency
Detector
Loop
Filter
Fref
VCO
RF
DDS
M
FRF = 2n
Fref
M
39
DDS Used in Translation Loop
Phase/
Frequency
Detector
Loop
Filter
Fref
VCO
RF
÷
N
Fclk
DDS
F
FRF = N Fref + M clk
2n
40
RF Upconversion Using Analog IQ Mixing
ADL537x
TxDAC
BPF
RF
I
I
DSP
CHANNEL
FILTER
AD977x
LO
S
0°
90°
BPF
PA
Q
Q
TxDAC
BPF
300MHz – 3.8GHz
41
RF Upconversion Using Digital IQ Mixing
QDUC =
QUADRATURE
DIGITAL
UPCONVERTER
N
I
I
DSP
CHANNEL
FILTER
AD9857
AD9957
NCO
Q
S
0°
90°
Q
N
DAC
IF TO 400MHz
(AD9957)
BPF
RF
BPF
PA
LO
42
RF Upconversion Using Dual DDS for LO
ADL5385
TxDAC
I
BPF
I
DSP
CHANNEL
FILTER
DUAL
DDS
AD977x
Q
RF
0°
S
90°
BPF
PA
Q
TxDAC
BPF
50MHz - 2.2GHz
43
On-Line DDS Tools
ADIsimDDS
44
DDS Design Tool Main Screen
45
DDS Design Tool: Tabular Display of Spurs
46
DDS Design Tool: Display Options
and Filter Selection
47
http://www.analog.com/dds
Click
‘More …’
to find
the cool
technical
papers
48
Summary
 DDS can be used to obtain a variety of precision waveforms
 Compared to other frequency generating techniques, a DDS has
the following advantages:
 Precise phase control without affecting frequency
 Precise frequency control without affecting phase
 Fast arbitrary phase changes
 Fast arbitrary frequency changes
 Precision modulation
 DDS has well known error characteristics
 Care must be taken designing the output analog circuitry
 Applications abound!
ADI makes some GREAT parts
49