von Neumann Architecture
CPU
CPU in von Neumann Architecture
CPU Registers
Arithmetic Logic Unit
Control Unit
Circuits for
Adder
Shifter
Multiplier
Divider
Control Processing Unit (CPU)
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
0000010100110000
Control Unit
0110100111100001
Program Counter
1011100110001100
00000011
ALU
Instruction Register
00110100
Control Processing Unit (CPU)
0100000000000111
0000000000011110
0000100000010000
0000000000000001
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
0000010100110000
Control Unit
0110100111100001
Program Counter
1011100110001100
00000011
ALU
Instruction Register
00110100
Control Processing Unit (CPU)
A few fast registers + math circuits
0100000000000111
0000000000011110
0000100000010000
0000000000000001
Lots of slow registers
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
000001010011000
Control Unit
000100111100001
Program Counter
000000110001100
00000000
ALU
Instruction Register
00000000
Control Processing Unit (CPU)
Fetch-Execute Cycle Runs Program
100000000000111
000000000000110
000000000010000
0000000000000001
Programs AND data
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
000001010011000
Control Unit
0000100111100001
Program Counter
000000110001100
00000001
ALU
Instruction Register
1010011000
Control Processing Unit (CPU)
Fetch-Execute Cycle Runs Program
100000000000111
00000000000110
000000000010000
0000000000000001
Programs AND data
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
000001010011000
Control Unit
0000100111100001
Program Counter
000000110001100
00000010
ALU
Instruction Register
100111100001
Control Processing Unit (CPU)
Fetch-Execute Cycle Runs Program
100000000000111
00000000000110
000000000010000
0000000000000001
Programs AND data
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
000001010011000
Control Unit
0000100111100001
Program Counter
000000110001100
00000011
ALU
Instruction Register
110001100
Control Processing Unit (CPU)
Fetch-Execute Cycle Runs Program
100000000000111
00000000000110
000000000010000
0000000000000001
Programs AND data
Von Neumann Architecture CPU
Random Access Memory
(RAM)
CPU Registers
Next time
we'll start
Control Unit
to run actual
Program Counter
00000011
ALU
Instruction Register
110001100
programs
using Hmmm
Control Processing Unit (CPU)
Fetch-Execute Cycle Runs Program
Programs AND data
How do programs execute?
Problem – a CPU does not execute instructions
directly from memory.
Instructions need to be brought into the
CPU from memory one at a time.
The fetch – execute cycle
while not halt instruction
Fetch instruction from memory and
place in Instruction Register(IR)
Add one to Program Counter(PC)
Decode instruction
Execute instruction
More Bits of the implementation…
An 8-bit register:
D Q
s
D Q
s
D Q
s
D Q
s
D Q
s
D Q
s
D Q
s
D Q
s
Registers are an integral part of every CPU
(Nothing more than collection of D Flip Flops!)
The PC register holds the memory address of the next instruction.
Program Counter
PC
The IR register holds the instruction to be executed.
Instruction Register
IR
Data registers can be used as the programmer wishes.
But who is this hypothetical programmer?
Reg3
Reg4
A Control Unit (CU) keeps all of the logic in sync and
keeps track of what needs to be done next…
CU
2
4
1
3
5
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
strobe
strobe for next instruction
D in
05 addn r3, 4
0
PC
Q out
0
0
0
0
1
0
1
8 address bits
read enable
RAM
flip-flop
strobe for all
IR bits
1
0
0
1
1
1
0
0 IR
8 data bits
2
CU
4
1
3
decode instruction
5
old value of Reg3 = 7
0
strobe to finish
instruction
(to all bits)
1
1
1
Reg3
ripple8
IR
1
0
0
1
1
1
0
7+4
0
8 output bits
The instruction
Argument 1
the register
00 = LOAD from memory Reg3
01 = STORE to memory
10 = add a constant to a reg. (addn)
11 = ADD a reg. to a reg.
Argument 2
the constant
4
Instruction Decoding Guide
1
0
1
1
the same Reg3
new value of Reg3 = 11
a Von Neumann machine