VHDL Basics
VHDL BASICS
OUTLINE
– Component model
– Code model
– Entity
– Architecture
– Identifiers and objects
– Operations for relations
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VHDL ET062G & ET063G
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COMPONENT MODEL
MODEL FOR DESCRIBING COMPONENTS
– External interface
– Internal function
Ports: external connections
to the component
VHDL-component
A
B
C
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The component’s
- Behaviour or
- Structure
X
Y
Function: a number of
parallel processes
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DESCRIPTION MODEL
VHDL-component
Declaration of entity
Interface
- Entity with ports
Declaration of architecture
Function
- architecture
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DECLARE THE INTERFACE OF THE VHDLCOMPONENT
MUX 2-1
a
y
b
entity mux2 is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
sel: in STD_LOGIC;
y: out STD_LOGIC;
);
end mux2;
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VHDL ET062G & ET063G
sel
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THE PORTS OF THE VHDL-COMPONENT
port defines inputs
and outputs
entity mux2 is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
sel: in STD_LOGIC;
y: out STD_LOGIC;
);
end mux2;
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VHDL ET062G & ET063G
in/out defines the mode
of the port
Determines the direction
of the dataflow
std_logic is the datatype
for the inputs and output
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PORTS IN VHDL
PORT-DECLARATION IS THE MOST IMPORTANT
THING IN THE ENTITY-DECLARATION
EACH PORT REPRESENTS
– The external pins of the component
An identifier that
EACH PORT HAS A
you create
– Port-name
Direction of data
– Mode
– Datatype
Which values to port
can be assigned
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THE MODES OF THE PORT
IN
OUT
BUFFER
INOUT
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The signal goes only in to the component and the value is
driven by another component.
The input signal is used on the right side in the assignment:
z <= a OR inport
The signal goes out from the component.
It is not possible to read the value of the output.
Is used on the left side in the assignment:
outport <= a OR b
The signal goes out from the component.
It is possible to read back the value of the output.
Can be used on both sides in the assignment:
buffer_port <= a OR b;
z <= buffer_port OR c;
The signal can go in both directions, either in or out
-The value of the signal can be read by the component
-The signal can be driven by other components
-Can be used in both sides in an assignment
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DESCRIBING THE FUNCTION IN THE
ARCHITECTURE
architecture mux2_arch of mux2 is
begin
mux2_1: process(a, b, sel)
begin
if sel = '0' then
y <= a;
else
y <= b;
end if;
end process mux2_1;
end mux2_arch;
Najeem Lawal, 2012
VHDL ET062G & ET063G
MUX 2-1
a
y
b
sel
In the architecture the
function is described:
If sel is 0 then the value of a is
put on the output y.
Otherwise (sel=1) the value of b
is put on the output y.
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DECLARATION OF THE ARCHITECTURE
Name of the architecture
begin … end for
the architecture
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architecture mux2_arch of mux2 is
begin
mux2_1: process(a, b, sel)
begin
if sel = '0' then
y <= a;
else
y <= b;
end if;
end process mux2_1;
end mux2_arch;
VHDL ET062G & ET063G
Name of the entity
Process
with sensitivity-list
Sequential
statements
(if-then-else) in the
process
begin … end
for the process
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STRUCTURE OF THE ARCHITECTURE
architecture name_arch of name is
Declaration of signals
begin
Parallella satser
Process 1
Signals are used for
communication between
components and parallel
statements.
Signals can only be declared at
architecture-level (not in
processes)
Parallel statements
Inside a process the execution is
sequential
Process 2
Parallel statements
end name_arch;
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VHDL ET062G & ET063G
Processes and parallell
statements are executed in
parallel
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EXAMPLE OF PARALLEL AND SEQUENTIAL
STATEMENTS
ENTITY ename IS
Ports( a, b, c: IN bit;
y, z, w: OUT bit;
Declarations
-- no variables allowed
END ename
ARCHITECTURE first OF ename IS
Declarations
-- no variables, but signals are OK
BEGIN
y <= a AND b;
PROCESS (a,b,c)
Declarations
-- no signals,
but variables are OK
VARIABLE v: bit;
BEGIN
v := (a OR b);
v := v AND c;
w <= a XOR v;
END PROCESS;
Parallel processes
Statements in processes are sequential
z <= c XOR b;
END first;
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IDENTIFIERS IN VHDL
IDENTIFIERS
– Are names of things that you create
– E.g. names for architectures, entities, processes,
variables, signals
– Rules for naming
• Cannot be a reserved word in VHDL (e.g. for, if)
• VHDL is case-insensitive
• First character must be a letter
• Last character cannot be underscore (_)
• Two consecutive underscores are not allowed
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VHDL ET062G & ET063G
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OBJECTS IN VHDL
OBJECTS CAN HOLD A VALUE
– Objects have class and type
• Class determines what kind of operations can
be performed on the object
• Type determines what values the object can
hold
– Objects can be initialized (only for simulation)
– They are declared in entity, architecture, process,
or package
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VHDL ET062G & ET063G
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CLASSES IN VHDL
SIGNAL
– Their values are changed as a function of time
– They have a signal-driver and can be seen upon as
a wire
VARIABLE
– Their values are changed immediately after
assignment
– No timing is related to variables
CONSTANT
– Their values cannot be changed
FILE
– Values to and from external file can be accessed
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DATA TYPES IN VHDL
VHDL HAS HARD REQUIREMENTS ON TYPING
– Objects of different types cannot be mixed
– Functions for type-conversion must be used
TWO MAIN CATEGORIES OF DATATYPES
– Scalar
• Can be assigned one single value
• Examples: enumeration, integer, float, physical
– Composite
• Can be assigned multiple values
• Examples: array, record
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SCALAR
ENUMERATION
– A list of discrete values the variable can be assigned to
– Ex: type weekday = (mon, tue, wed, thu, fri,
sat, sun);
INTEGER
– A set integers – positive or negative
– A pre-defined datatype
– Integer is of 32-bits with sign –231 to +(231-1)
– When describing hardware a limited range can be used
• Ex: variable num: integer range –64 to 64
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SCALAR
FLOATING-POINT
– Pre-defined datatype is real
– 32-bits single precision
– Is never used for describing hardware
• Will result in too complex hardware
PHYSICAL
– Datatype for physical units
• Ex. time, mA, Volt
• Has no meaning for describing hardware
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VHDL ET062G & ET063G
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EXAMPLES OF ENUMERATED DATATYPES
PRE-DEFINED TYPES (1076)
– type boolean is (FALSE, TRUE);
– type bit is (’0’,’1’);
PRE-DEFINED TYPES (1164)
– Std_logic
– Std_ulogic
– Arrays of these types and sub-types
– Access to these types by including:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
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STD_LOGIC
Definition av std_logic
type std_ulogic is (
‘U’, -- Uninitialized
‘X’ -- Forcing unknown
‘0’ -- Forcing zero
‘1’ -- Forcing one
‘Z’ -- High impedance
‘W’ -- Weak unknown
‘L’ -- Weak zero
‘H’ -- Weak one
‘-’);-Don’t care
subtype std_logic
is resolved
std_ulogic;
library IEEE;
use IEEE.std_logic_1164.all;
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First in the VHDL to include libraries
(packages)
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COMPOSITE DATA TYPES
ARRAYS
– Examples of declarations of 8-bit vectors
signal s1: bit_vector(7 downto 0);
variable v1: bit_vector(7 downto
0);
– Assignment of the bit vector 11010010
s1 <= ”11010010”;
v1 := ”11010010”;
Least significant bit
Most significant bit
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VHDL ET062G & ET063G
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COMPOSITE DATA TYPES
EX: TWO-DIMENSIONAL ARRAY
– type table6x2 is array (0 to 5, 1 downto 0) of bit;
– constant mytable: table6x2 :=
(”00”,”01”,”10”,”11”,”01”,”01”);
1
0
0
1
2
3
4
5
’0’
’0’
’0’
’1’
’1’
’0’
’1’
’1’
’0’
’1’
’0’
’1’
EX: BIT VECTORS FOR BINARY, OCTAL AND HEXADECIMAL
NUMBERS


X”A3”-- = B”1010_0011” for a 8-bits vector
O”27”-- = B”010_111” for a 6-bits vector
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ATTRIBUTE
ATTRIBUTE
– Holds information about a signal, variable, data type,
function.
– Example #1
type bitcount is integer range –3 to +5;
-3
-2
-1
0
+1 +2
bitcount’left
bitcount’right
bitcount’low
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+3 +4 +5
bitcount’high
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ATTRIBUTE
– Example #2
type byte is array (7 downto 0) of std_logic;
7
6
5
4
3
2
1
byte’left
0
byte’right
byte’low
byte’high
i goes from 7 down to 0

Example #3
for i in byte’high downto byte’low loop
v_byte(i) := ’1’;
end loop;
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VHDL ET062G & ET063G
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OPERATORS IN VHDL
OPERATORS FOR RELATIONS
ARITHMETIC OPERATIONER
Symbol
=
/=
<
>
<=
>=
Symbol
+
*
/
abs
rem
mod
**
Operation
equal
Un-equal
Less than
Greater than
Less-equal
Greater-equal
Operation
addidion
subtraktion
multiplikation
division
Absolute value
remainder
modulus
exponent
Supported by
synthesis tools
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ESSENTIALS IN VHDL
Library ieee;
Use ieee.PACKAGE_NAME.function
entity entity_name is
end entity entity_name;
port (
port_name : MODE(e.g. IN) DATA_TYPE(e.g. STD_LOGIC)
);
architecture arch_name of entity_name is
SIGNAL sig_name : data_type := initial_value;
begin
JKHHJ
parallel statements;
end architecture arch_name;
pro_label: process( sensitivity list)
variable var_name : data_type := initial_value;
Begin
sequential statements;
end process pro_label;
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VHDL ET062G & ET063G
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ESSENTIALS IN VHDL
Library ieee;
Use ieee.std_logic_1164.ALL;
entity mux2 is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
sel: in STD_LOGIC;
y: out STD_LOGIC;
);
end mux2;
architecture mux2_arch of mux2 is
begin
mux2_1: process(a, b, sel)
begin
if sel = '0' then
y <= a;
else
y <= b;
end if;
end process mux2_1;
end mux2_arch;
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VHDL ET062G & ET063G
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ESSENTIALS IN VHDL
architecture struct_arch of entity_name
COMPONENT component_name
PORT(
port_name : MODE data_type;
);
END COMPONENT;
SIGNAL connecting signale : data_type := initial_value;
Begin
instance_name : component_name PORT MAP (
port_name => connecting_signal,
);
End architecture struct_arch;
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END OF LECTURE 2
Outline
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Najeem Lawal, 2012
Component model
Code model
Entity
Architecture
Identifiers and objects
Operations for relations
VHDL ET062G & ET063G
29