International Journal of Science, Engineering and Technology Research (IJSETR)
Volume 1, Issue 1, July 2012
Design and Simulation of FPGA Based 16-QAM
Mapper and Demapper Using VHDL
Chaw Su Nandar Hlaing

Abstract— This paper presents the simulation results of
16-QAM mapper and demapper modulation schemes . The
results are shown by using Very High Speed Integrated
Circuit(VHSIC) Hardware Description Language(HDL),
known as VHDL, in Quartus 7.2 software. By using VHDL,
Field Programmable Gate Arrays(FPGAs) can be used in many
different purposes. FPGAs are very efficient devices for
different kinds of areas in electronic field. In this paper, the
16-QAM mapper and demapper is designed by using VHDL and
it is purposed for FPGA devices. The transmitter of 16-QAM
composed of serial-to-parallel converter, temporary register,
clock divider and mapper. The receiver of 16-QAM composed of
demapper, temporary register, parallel-to-serial converter,
clock divider and displays of output. Quartus II 7.2 (32-bit) will
be used for simulation, functional verification, testing and
demonstration of the implemented system.
Index Terms—16-QAM, FPGA, System mapping, demapping,
VHDL
I.
INTRODUCTION
stands one of the best selections which let to produce high
execution, high integrated density and dedicated purpose integrated
circuits (IC).With elasticity in design and precision in timing
control, FPGA creates it easier and more accurate in simulating,
testing, validating and implementing components. Modulation
technique such as QAM(Quadrature Amplitude Modulation) is one
of the widely used modulation techniques in cellular communication
because of its high efficiency in power and bandwidth. QAM
modulation is combined ASK(Amplitude Shift Keying) and
PSK(Phase Shift Keying).16-QAM is a kind of digital modulation
techniques which transfers four bits per symbol on two orthogonal
carriers; one in phase and other in quadrature phase. Therefore data
rate is bigger by a factor of four.
In this research, we grants a diagram of a complete 16-QAM mapper
and demapper and the simulation results based on Quartus II 7.2(32
bits) in VHDL.The mapper and demapper are performed in the same
FPGA kit. Both mapper and demapper are occupied into account in
this model using VHDL (Very High Speed Integrated Circuit
Hardware Description Language).The remaining of this research
obtainable as QAM transmitter, QAM receiver, implemented results
and conclusions.
II. QUADRATURE AMPLITUDE MODULATION
The process in which some parameters of a periodic waveform
are varied and that signal is used to convey a message. There are two
basic types of modulation: analog modulation and digital
modulation. Generally, if the variation is continuous in accordance
to the input analog signal, the modulation technique is known as
analog modulation. If the variation is discrete, the modulation is
known as digital modulation. Digital modulation is less complex,
more secure and more efficient in long distant transmission.
Although there are many types of digital modulation methods, only
QAM modulation methods are used here. It is required VHDL codes
for designing and Quartus 7.2 software for simulation. 16-QAM
mapper and demapper technique is implemented on Cyclone II
family of FPGA devices in this journal.The FPGA technology has
been involving a considerable role in portable and mobile
communication because of the features of elasticity, exactness and
configurability in designing and implementation. VHDL(Very High
Speed Integrated Circuit(VHSIC) Hardware Description
Language(HDL)) is intended for describing and modeling a digital
system at various levels and is an extremely complex language. The
system can be utilized in typical Wi-max system and any other QAM
based communication systems.
The development of mobile and portable communications needs
high performance of hardware systems and affectivity and flexibility
in design and implementation. In this conditions, FPGA technology
Manuscript received Oct 15, 2011.
Chaw Su Nandar Hlaing, Departmen of Electronic Engineering,
Mandalay Technological University., (e-mail: chawsunandarhlaing@
gamil.com).
Second Author name, His Department Name, University/ College/
Organization Name, City Name, Country Name, Phone/ Mobile No.,
(e-mail: [email protected]).).
QAM is one of widely used modulation techniques because of
its efficiency in power and bandwidth. In QAM system, two
amplitude-modulated (AM) signals are combined into a single
channel, thereby doubling the effective bandwidth. However, it
must also be noted that when using a modulation technique such as
64-QAM, better signal-to-noise ratios (SNRs) are needed to
overcome any interference and maintain a certain bit error ratio
(BER).Quadrature amplitude modulation (QAM) stands a
modulation scheme in which data is sent by varying both amplitude
and phase of the carrier signal, one exactly 90 degrees out of phase
with respect to the other. Generally this two carrier waves are taken
which are orthogonal to each other and occupy the same frequency
band and differ by a 90 degree phase shift, each can be modulated
independently, transmitted over the same frequency band, and
separated by demodulation at the receiver. Four bits are grouped by
taking two bits from each carrier to form a symbol. The number of
possible symbol is 24 = 16 and one of these 16 possible signals is
transmitted at each symbol period. For a given available bandwidth,
QAM enables data transmission at twice the rate of standard pulse
amplitude modulation (PAM) without any degradation in the bit
error rate (BER). QAM and its derivatives are used in both mobile
radio and satellite communication systems. These two carrier waves
represent the in-phase (I) and Quadrature-phase (Q) components of
our signal. Individually each of these signals can be represented as:
I = A cos (φ) and Q = A sin (φ).
Note that the I and Q components are represented as cosine and
sine because the two signals are 90 degrees out of phase with
one another. As with many digital modulation techniques, the
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All Rights Reserved © 2012 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR)
Volume 1, Issue 1, July 2012
constellation diagram is a useful representation. It provides a
graphical representation of the complex envelop of each
possible symbol state. The constellation diagram of 16-QAM
is shown in Figure 1. The constellationconsists of a square
lattice of signal points.The general form of a 16-QAM signal
can be defined as:
2 E min
2 E min
ai cos 2f 0 (t ) 
bi sin 2f 0 (t )
Ts
Ts
0  t  Ts , i  1, 2,3,...,16
si (t ) 
where Emin is the energy of the signal with the lowest
amplitude, ai and bi are a pair of independent integers
Figure Block diagram of QAM transmitter
chosen according to the location of the particular signal
point,f0 is the carrier frequency, Ts is the symbol period.
IV. QAM RECEIVER
The block diagram consists of demapper, temporary
register, parallel-to-serial converter, clock divider and
displays of outputs. Demapper performs the reverse function
of the mapper which converts the real and imaginary 8-bits
signals from transmitter into four bits binary values and stole
in temporary register. Parallel-to-serial converter converts
four bit binary values in register into serial data in output by
four clock pulse.
Figure 1. 16-QAM Constellation Diagram
If rectangular pulse shapes are assumed, the signal si (t)
may be expanded in terms of a pair of basis functions defines
as
1 (t ) 
2 (t ) 
2
cos(2 f 0t ) 0  t  Ts .
Ts
2
sin(2 f 0t ) 0  t  Ts .
Ts
The coordinates of the
ai
Figure. Block diagram of QAM receiver
TABLEI
16-QAM SYSTEM MAPPING
ith message points are
Emin and bi Emin where ( ai , bi )is an element of the 4
by 4 matrix shown below.
(3,3)(1,3)(1,3)(3,3)

(3,1)(1,1)(1,1)(3,1)

( ai , bi )= 

(3, 1)(1, 1)(1,  1)(3,  1) 


(3, 3)(1, 3)(1,  3)(3,  3)
III. QAM TRANSMITTER
he block diagram consists of serial-to-parallel converter,
temporary register, clock divider and mapper. We use random
data source to capture all possibilities of data statistic at the
rate of four clock periods. Clock divider divides one clock
pulse for four clock pulses. Serial-to-parallel converter
converts data input to four bit binary values. And this four bit
binary values store temporarily in register. Mapper takes four
bit binary values as inputs and maps them into real and
imaginary 8-bits signals.
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All Rights Reserved © 2012 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR)
Volume 1, Issue 1, July 2012
V. SIMULATION RESULTS
Figure 3. VHDL source code of 16-QAM mapper and
demapper in QuartusII 7.2 (32 bits)software
Figure-System block diagram of 16-QAM mapper and
demapper in QuartusII 7.2 (32 bits)software
Figure 4.Simulation result of 16-QAM mapper and demapper
in QuartusII 7.2 (32 bits)software
Figure 1.Flow summary of 16-QAM mapper and demapper
in QuartusII 7.2 (32 bits)software
Figure 5.Simulation result of 16-QAM mapper and
demapper in QuartusII 7.2 (32 bits)software
Figure 2.VHDL source code of 16-QAM mapper and
demapper in QuartusII 7.2 (32 bits)software
The simulation results are displayed as follows: first of all,
we join system blocks with VHDL language andcan declared
IEEE library and package which allow us to add additional
types, operators, functions, etc. to VHDL and then declared
entity which has input and output signals of the circuit in
figure2.Figure 1shows flow summary of the device after
simulation and figure 3 describes that if reset pin is1,our
simulation results do not work. If reset is 0, our simulation
results work with Table1in our VHDL program. If input serial
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All Rights Reserved © 2012 IJSETR
International Journal of Science, Engineering and Technology Research (IJSETR)
Volume 1, Issue 1, July 2012
data is 1111, then real output signal is 11111101 and
imaginary output signal is 11111101 and then input is
1110,real output is 11111101 and imaginary output is
11111111 and so on. In demapper section, if real and
imaginary signals are 11111101 and 11111111,then output
signal is 1110and so on.
I. CONCLUSIONS
This paper presents mapping and demapping of 16-QAM
using Quartus II 7.2 (32bits) with VHDL language. By using
serial-to-parallel converter in 16-QAM,serial input data is
converted into 4 bits parallel data and this is decomposed into
real and imaginary 8 bits data by using mapper. And in
demaper section, real and imaginary 8bits output in mapper is
demapped into 4 bits binary values and changed serial data
(original data signals) by using parallel-to-serial converter.
By using VHDL on FPGA, the cost effective and high
quality devices can be created. In this paper, the VHDL codes
for signed binary number and DAC interface are used to be
able a complete process. The code to integrate all the codes is
also important. The review of different research works on
16-QAM demonstrates that models planned so far are taking
only some of the design issues into thought each. Still
research required to intend a complete 16-QAM model with
the purpose to contribute in the field of digital modulation.
ACKNOWLEDGMENT
Author would like to express her appreciation to her head
of department, her supervisor Dr.HlaMyoTun, Associate
Professor and, cosupervisorDr.KyawSoeLwin for their
precious guidance, supports and all the teachers and friends
from the Department of Electronic Engineering , Mandalay
Technological University.
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