Reactive ion etching induced damage with gas mixtures CHF3/O2
and SF6/O2
W. Wu and P. K. McLarty
Center for Advanced Electronic Materials Processing, North Carolina State University, Raleigh,
North Carolina 27695
~Received 8 November 1993; accepted 22 October 1994!
In this work, reaction ion etching ~RIE! induced damage and its impact on device performance have
been characterized and evaluated using a variety of characterization techniques for two
technologically important gas mixtures: CHF3/O2 for selective oxide etching, and SF6/O2 for
selective poly Si or crystalline Si etching. Current–voltage characteristics of Al/Si Schottky diodes
fabricated on the RIE exposed Si surface reveal significant barrier height shifts for the CHF3/O2
process while showing little change for the SF6/O2 processes. Carrier generation lifetime is degraded
by at least one order of magnitude, with the degradation due to CHF3/O2 processes being more
severe. Scanning electron microscopy and Auger electron spectroscopy support the idea that the
defects that give rise to the altered electrical behavior are most likely Si lattice damage instead of
metal contamination and/or morphologic modification. Rapid thermal annealing of the CHF3/O2
etched samples has a negative effect on I – V recovery precluding simple application of RTA for
removing RIE damage. In the RIE exposed oxide, the two distinctively different gas mixtures induce
very similar C – V and Si/SiO2 interface property changes, suggesting that the high energy photons
present in the plasma glow are the most probable source of damage in the oxide. © 1995 American
Vacuum Society.
I. INTRODUCTION
Reactive ion etching ~RIE! is by far the most widely used
dry etching technology because of its capability of high anisotropy required by today’s very large scale integration
~VLSI! device fabrication. Unfortunately, energetic ions and
photons associated with the RIE process may cause damage
to the wafer being etched and thus degrade the device performance and lower the overall yield. As the demand for
higher performance VLSI circuits continuously pushes the
device geometry towards the deep submicron regime, accompanied by thinner gate oxide and shallower junctions, the
RIE damage effect becomes more and more prominent and
hence has drawn much attention evidenced by the increasing
number of publications on this subject. References 1–3 are
review articles in this area. Although a considerable amount
of work has already been done, it is far from enough due to
the extreme complexity of the RIE process which is characterized by a large number of variables and a strong dependence of the resulting damage on these many process
parameters.4 Because of the complexity, it is not surprising
that, more often than not, results from different groups show
a wide variation and even contradiction. For example, the
reported depths of RIE induced deep levels observed with
deep-level transient spectroscopy ~DLTS! range from hundreds of angstroms to several micrometers.5–7 Metal contamination is found to be the cause of metal–oxide semiconductor ~MOS! capacitor lifetime degradation by some
authors8 but excluded by others.9 Obviously, more work
needs to be done in order to clarify many of the ambiguities.
In an attempt to confirm and expand some aspects of the
existing knowledge base of RIE induced defects, two technologically important etch gas mixtures were chosen for this
work. They are CHF3/O2 , which selectively etches oxide,
67
J. Vac. Sci. Technol. A 13(1), Jan/Feb 1995
and SF6/O2 , which selectively etches poly or crystalline Si.
In the comparative experiment, however, the two gas mixtures were used in parallel to etch both oxide and silicon,
regardless of their actual application in VLSI fabrication.
The characterization methods used include both electrical
~I – V, C – t, C – V! and analytical @scanning electron microscopy ~SEM!, Auger electron spectroscopy ~AES!# techniques.
II. EXPERIMENT
Samples were prepared on commercially available 4-in.
^100& oriented Si prime wafers. The p-type wafers were boron doped with a resistivity of 1–2 V cm and the n-type
wafers were phosphorus doped with resistivity of 2– 4 V cm.
The backsides of all of these wafers were randomly scribed
to facilitate later ohmic contact formation. A blanket dry oxide about 450 Å thick was first grown on all these wafers at
950 °C after a standard RCA cleaning process. On some of
the wafers this oxide was then 50% overetched by RIE so
that the Si substrate was exposed to the RIE plasma and on
others, 250 Å of oxide was removed to determine the effect
of exposing the oxide to RIE. The RIE system used in this
work was a parallel-plate diode type Semi Group 1000 TP,
with an electrode area of 730 cm2. The 13.56 MHz rf power
is supplied to the water-cooled cathode. During the etching
process special care was taken to avoid metal contamination.
These measures included covering the metallic cathode with
a quartz plate and using silica wafer sleeves. These sleeves
were about 1 cm high compared to the 1.6 mm mean-free
path under the 30 mTorr etching pressure. Table I summarizes the etching conditions used in this study. Under the
0734-2101/95/13(1)/67/6/$1.00
©1995 American Vacuum Society
67
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W. Wu and P. K. McLarty: RIE induced damage
68
TABLE I. RIE processes and their parameters.
Process
Gas flow
~sccm!
Power
~W!
Pressure
~mTorr!
V ca
~V!
CHF3/O2
SF6/O2
20/2
15/10
200
200
30
30
2454
2366
a
The cathode voltages V c shown were the stabilized reading after the plasma
had been turned on for a few seconds.
conditions shown there the oxide and silicon etch rates were
200 and 50 Å for the CHF3/O2 gas and 360 and 2200 Å for
the SF6/O2 gas, respectively.
After RIE of all wafers, a few of them were reserved for
the analytical characterization. Two types of devices were
fabricated for the electrical measurements. They were
Schottky diodes for I – V measurements, and MOS capacitors
for C – V and C – t measurements, respectively. For Schottky
diode fabrication, the wafer backside was first stripped of the
oxide and Al metalized, followed by a 400° C forming gas
anneal in N2/H2 ambient for 30 min to form the ohmic contact. Then thermally evaporated Al was deposited through a
shadow mask onto the frontside of the wafer. Immediately
before loading these wafers into the vacuum chamber for
metalization, a premetalization cleaning ~backdoor etch! was
performed to remove any native oxide. MOS capacitors for
C – t lifetime measurements were made by chemical vapor
deposition ~CVD! of the low temperature oxide ~LTO! at
410° C as the gate oxide on n-Si substrate after the original
thermal oxide had been overetched by RIE. This process was
intended to preserve the damaged Si surface after RIE. Thermal oxide was grown on a CHF3/O2 etched wafer for comparison. The CVD oxide was densified at 900 °C for 2 min in
a N2 ambient before depositing the gate metal Al through a
shadow mask. After backside metalization with Al, a forming
FIG. 1. I – V characteristics of Al/Si Schottky contacts fabricated on Si surgas anneal was performed at 400 °C for 30 min in N2/H2
faces exposed to RIE. ~a! p-Si; ~b! n-Si.
ambient. The control samples were made by substituting
only the RIE step with a wet chemical etch ~BOE!. On the
can be readily explained by a change in the barrier heights of
under etched thermal oxides, MOS capacitors were fabrithe Schottky diodes. The thermionic model for a Schottky
cated by evaporating 4000 Å of Al through a shadow mask.
diode predicts10
After blanket evaporation of Al on the backside of the wafer,
a forming gas anneal was performed at 400 °C for 30 min in
I5I S @ exp~ qV D /kT ! 21 # ,
~1!
N2/H2 ambient. These capacitors were used to investigate the
2
where I S 5A eff A **T exp~2q f B /kT! and V D is the actual
effect of exposing the thermal oxide to RIE.
voltage drop across the Schottky junction.
For external forward bias V.kT/q, but not too large so
that V5V D 2IR'V D still holds,
III. RESULTS AND DISCUSSION
I5I *
~2!
S exp@ q ~ V D 2 f B ! /kT #
A. I – V characteristics
which increases rapidly after V> f B . I *
S is defined as
2
**
[A
A
T
.
Hence
the
forward
threshold
voltage of the
I*
I – V measurements were made on both p- and n-type
S
eff
Schottky diode is determined by the barrier height. The reSchottky diodes. From the I – V plots shown in Fig. 1, it is
verse leakage current I r 5I *
clearly seen that for the p-type substrate @Fig. 1~a!#, the RIE
S exp~2q f B /kT! can be obtained
from the same equation by noting V D !0.
with CHF3/O2 has significantly increased the forward threshFrom the above it is clear that an increase in the barrier
old voltage and at the same time reduced the reverse leakage
height on the p-type sample and a decrease in the barrier
current when compared to the control sample. For the n-type
height on the n-type sample can explain the observed behavsample the opposite behavior is observed with the CHF3/O2
ior. This systematic barrier height change, referred to as baretch decreasing the forward threshold voltage and signifirier height shift, is a commonly observed RIE damage effect
cantly increasing the reverse leakage current. This behavior
J. Vac. Sci. Technol. A, Vol. 13, No. 1, Jan/Feb 1995
69
W. Wu and P. K. McLarty: RIE induced damage
and is sometimes attributed to a surface charge layer related
to the structural bonding damage.2 An increase of the barrier
height for holes in p-type material and a decrease of the
barrier height for electrons in n-type material suggest that the
charge is positive.
Another possible reason for the degradation of the properties of the n-type Schottky diode is through the introduction of defects resulting from the RIE processes. It is rather
unlikely however that the increase in reverse leakage current
in the n-type sample is caused by an increase in generation
current due to lifetime degradation, since the same etching
conditions on the p-type sample decreases, not increases, the
reverse leakage current. In fact, the generation current can be
estimated by evaluating I g 5(qn i WA)/ t g , where the depletion width W is about 1 mm at 5 V reverse bias for the
doping of 1015 cm23, the area of metal dot A is 0.003 17
cm2, and the unit charge q and the Si intrinsic carrier concentration n i are both known constants. Even for tg as short
as 10210 s, which is equivalent to gold doping of 1017
cm23,10 I g is still only about 1 mA, incomparably smaller
than the reverse leakage currents observed here. Hence I g is
not the major contributor to the reverse leakage current for
either n- or p-type substrates. A few comments should be
made about the leakage currents in the n- and p-type control
samples. The leakage currents observed in the p-type control
samples are significantly larger than those observed in the
n-type control samples. This is to be expected because of the
difference in the barrier heights of the Schottky diodes. The
leakage currents of both samples are however higher than
that previously observed for similar diodes. This increased
leakage current might be caused by the presence of a thin
interfacial layer at the metal semiconductor interface due to
the lack of substrate heating during metal evaporation.11
In both p- and n-type samples, RIE with SF6/O2 results in
very little deviation of the I – V characteristics from that of
the control sample. This is believed to be due to the much
faster etch rate of SF6 on Si compared to CHF3/O2 resulting
in less accumulation of the residual damage.1
Rapid thermal annealing ~RTA! was performed on the
CHF3/O2 etched samples to determine its effectiveness in
removing the damage. These anneals were performed in an
AG Heatpulse rapid thermal annealing furnace at 1000 °C
for 30 s in an argon ambient. As is shown by Fig. 2, RTA has
negative effect on I – V recovery, agreeing with the results of
Ransom et al.12 obtained with closely related etching gases
CF4140% H2 . It has also been reported that RTA was found
to be effective in recovering the I – V characteristics of
Schottky diodes made on CCl4 etched silicon.13 Here it was
suggested that RTA can be used to achieve electrical property
and structural recovery after dry etching if no substantial film
layer is present after RIE. The results of Auger analysis presented in Sec. III C indicates the presence of increased carbon on the surface of the CHF3/O2 etched wafers. This increased carbon might indicate the presence of a polymer
layer and thus could explain the RTA results obtained here.
The control sample that was subjected to an RTA step after
the oxide wet etching, labeled as ‘‘RTA’’ on the plot legend,
shows no difference in I – V characteristics from the control
sample without RTA. This suggests that the RIE damage efJVST A - Vacuum, Surfaces, and Films
69
FIG. 2. I – V characteristics of Al/Si Schottky contacts fabricated on Si surfaces subjected to different processes showing the effect of RTA on CHF3/O2
RIE induced damage. ~a! p-Si; ~b! n-Si.
fect indicated by I – V deterioration can be enhanced by RTA,
although RTA itself alone produces no noticeable damage.
B. Generation lifetime
The lifetime was measured using the pulsed capacitor
method proposed by Zerbst.14 Table II shows the generation
lifetime measurement results. As is clearly seen, RIE degrades the lifetime by at least one order of magnitude. RIE
TABLE II. Generation lifetimes of the n-Si substrate degraded by RIE.
Process
Control
SF6/O2
CHF3/O2
CHF3/O21300 Å
Thermal oxide
Generation lifetime ~s!
~2.8061!31024
~2.9660.4!31025
~1.7260.5!31025
~1.0660.5!31024
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W. Wu and P. K. McLarty: RIE induced damage
TABLE III. Relative carbon concentration from AES on Si surfaces subjected
to different processes.
Sample
Control ~wet etch!
RIE ~CHF3/O2!
RIE ~SF6/O2!
Wet etch1RTA
RIE ~CHF3/O2!1RTA
Relative C
concentration
1
1.35
1
0.706
1.18
with CHF3/O2 is again shown to produce more damage than
RIE with SF6/O2 on Si, which can be accounted for by
deeper defect profile produced by RIE with CHF3/O2 due to
its extremely slow etch rate of Si.
It is interesting to note that regrowing 300 Å of thermal
oxide at 950 °C in dry oxygen on the CHF3/O2 etched
sample, which consumed 132 Å of Si, has recovered the
lifetime by more than one order of magnitude. The recovered
lifetime almost reaches the value of the control suggesting
that majority of the RIE induced defects that degrade lifetime
have evolved out of the Si during the oxidation. It is unlikely
that the observed lifetime recovery during oxide regrowth
was due entirely to the thermal annealing, as the densification step for devices with CVD gate oxide was performed at
900 °C for a nominal time of 2 min. The actual time was
much longer because of the plentiful time margin for the
furnace temperature ramp-up ramp-down. Despite this thermal process, the wafers exposed to RIE still exhibit lifetime
degradation, as previously mentioned, by at least one order
of magnitude. This above suggests that the majority of the
damage responsible for the lifetime deterioration in these
samples probably exists within approximately 132 Å of the
silicon surface.
C. AES and SEM results
In order to detect any surface contamination by foreign
impurities, which may also cause the altered electrical characteristics, AES surface scans were performed on RIE exposed p-Si wafers. Under AES’s detection limit, which is
normally around 1019 –1020 atoms/cm3, no traces of metals
were observed on all of the samples tested. While it is possible that metallic impurities sputtered from the chamber inner wall or cathode in concentrations much less than 1019
atoms/cm3 could cause the observed lifetime degradation, no
such impurities were detected using DLTS which for current
doping levels has a detection limit of about 1012 atoms/cm3.
This suggests that the damage introduced by both CHF3/O2
and SF6/O2 RIE originates from the crystal structural damage
as a result of energetic ion bombardment, rather than the
metals sputtered from the chamber inner wall or cathode.
It should be noticed from the AES data in Table III that
the CHF3/O2 etched Si surface contains more C than the
control sample which was wet etched by BOE, suggesting
the formation of carboneous residual layer at the surface by
CHF3/O2 RIE. In addition, RTA under the same conditions as
described previously, reduces the C concentration on both
dry etched and wet etched Si surfaces. The reason for this
J. Vac. Sci. Technol. A, Vol. 13, No. 1, Jan/Feb 1995
70
behavior is not clear at the present time but it is believed that
it might be due to C diffusion from the surface into the bulk
substrate and/or dissipation via evaporation. It is also not
clear if C plays any role in the Schottky diode barrier height
shift or alteration of other electrical behavior. There is, however, strong evidence showing that C alone should not be the
primary cause. First, it was reported that RIE by a noncarboneous gas, such as NF3 , could still produce a significant
barrier height shift.15 Second, it has been shown that such a
barrier height shift exists even after the removal of the polymer layer.8 Finally, in our experiment, RTA on the wet etched
sample was found to have little effect on the I – V characteristics. It is not clear either whether the reduction in surface C
concentration, presumably due to possible C in-diffusion under heat, is responsible for the negative effect of RTA on
I – V recovery for CHF3/O2 etched sample.
SEM was performed on these samples, and no morphologic abnormality was observed. Within the resolution of the
SEM measurement, this would tend to suggest that morphologic changes in the silicon are not responsible for the altered
electrical characteristics.
D. RIE induced defects in SiO2
In order to evaluate the RIE damage effect on the oxide,
RIE exposed thermal oxide ~underetch! was used as the gate
oxide for MOS capacitors. These capacitors were subjected
to a constant current Fowler–Nordheim stress. This stress
was performed with the capacitors biased in accumulation
which, for the n-type substrates used, results in electron injection from the substrate. The charge ~C/cm2! was calculated by measuring the time for which each constant current
stress was applied. After passing a predetermined amount of
charge through the oxide, the interface state density ~D it! and
the threshold voltage ~V th! were measured using Keithley
simultaneous C – V measurement system. As is shown in
Figs. 3 and 4, without stress, the MOS capacitors with a RIE
exposed gate oxide exhibited almost identical C – V characteristics and D it values when compared to the control. The
existing damage, however, manifested itself after the stress
was applied. The MOS capacitors with a RIE exposed gate
oxide showed deterioration in the C – V characteristics and
an increase in D it , which became more severe for larger
amounts of charge, while the control device with wet etched
gate oxide showed much less change in the measured properties. It should also be noted that the majority of the degradation took place through an increase in D it with very little
trapping effects observed.
A comparison of the middle and bottom plots in the two
figures reveals unusual similarity between these two
samples, which were exposed to two distinctively different
RIE processes with varying oxide etch rates. This is in contrast to the previously discussed case of silicon where the
observed damage is very process dependent. Similar behavior has been previously observed after exposing oxide to RIE
with different process gases and conditions than those used
here.16 The results obtained here strongly support the idea
presented earlier that the observed oxide damage results from
the presence of penetrating photons rather than by bombard-
71
W. Wu and P. K. McLarty: RIE induced damage
FIG. 3. MOS capacitor HF C – V after the Fowler–Nordheim stress for oxides exposed to various etching processes. ~a! Wet etch; ~b! SF6/O2 ; ~c!
CHF3/O2 .
16
ment of the high energy reactive ions. This radiation would
be present in all RIE processes used here and could account
for the observed process independence.
IV. CONCLUSIONS
It was shown in this work that RIE creates near-surface
damage on exposed Si. From I – V measurements, Schottky
diodes fabricated on the RIE exposed Si surface showed systematic shifts of the barrier height, i.e., lower for n-Si and
higher for p-Si, suggesting the presence of a positive surface
charge layer associated with intrinsic bonding damage. RTA
JVST A - Vacuum, Surfaces, and Films
71
FIG. 4. D it of SiO2/n-Si interface after the Fowler–Nordheim stress for
oxides exposed to various etching processes. ~a! Wet etch; ~b! SF6/O2 ; ~c!
CHF3/O2 .
had negative effect on the I – V recovery of the CHF3/O2
etched sample. Using pulsed MOS capacitor measurements,
the generation lifetime was found to be degraded by RIE,
implying introduction of generation-recombination centers in
the near-surface region of the Si substrate. AES and DLTS
results suggested that these defects were not caused by metal
contamination. It was also observed that the RIE damage
effects on Si were highly process dependent. In the oxide
that was exposed to the RIE plasma, the two distinctively
different gas mixtures induced very similar C – V and Si/SiO2
interface property changes, which can be explained by the
penetrating photons in the plasma glow being the common
source of damage to the oxide.
72
W. Wu and P. K. McLarty: RIE induced damage
ACKNOWLEDGMENTS
The authors would like to thank Dr. Raymond W. Hammaker, and Joan N. O’Sullivan of Microelectronics Lab,
N.C. State University, for their assistance in device fabrication. This work has been partially supported by the NSF
Engineering Research Centers Program through the Center
for Advanced Electronic Materials Processing ~Grant No.
CDR 8721505!.
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