Outline
FINITE-STATE MACHINE
OPTIMIZATION
c Giovanni De Micheli
c GDM
Modeling synchronous circuits:
{ State-based models.
{ Structural models.
Stanford University
State-based optimization methods:
{ State minimization.
{ State encoding.
Synchronous Logic Circuits
Modeling synchronous circuits
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Interconnection of:
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{ Combinational logic gates.
{ Synchronous delay elements:
{ No direct combinational feedback.
{ Single-phase clocking.
{ Model circuits as nite-state machines.
{ Represent by state tables/diagrams.
{ Apply exact/heuristic algorithms for:
E-T or M-S registers.
Assumptions:
State-based model:
State minimization.
State encoding.
Structural models:
{ Represent circuit by synchronous logic network.
{ Apply:
Retiming.
Logic transformations.
Formal nite-state machine model
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State-based optimization
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FSM Specification
A set of primary inputs patterns X .
A set of primary outputs patterns Y .
A set of states S .
State Minimization
A state transition function:
{ : X S S.
State Encoding
!
An output function:
{ : X S Y for Mealy models
{ : S Y for Moore models.
Combinational Optimization
!
!
State minimization
for completely specied FSMs
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State minimization
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the corresponding output sequences match.
Theorem:
{ Two states are equivalent i:
Incompletely specied nite-state machines :
{ Unspecied transitions and/or outputs.
{ Intractable problem.
Equivalent states:
{ Given any input sequence
Completely specied nite-state machines :
{ No don't care conditions.
{ Easy to solve.
they lead to identical outputs and
their next-states are equivalent.
Equivalence is transitive:
{ Partition states into equivalence classes.
{ Minimum nite-state machine is unique.
Example
INPUT
0
1
0
1
0
1
0
1
0
1
3
{ Rene partition blocks.
At convergence:
{ Blocks identify equivalent states.
4
0/0
1/0
1/1
1/1
2
Algorithm
Stepwise partition renement.
Then:
1
1/1
0/1
{ All states in the same partition block.
0/0
0/1
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Initially:
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0/1
STATE N-STATE OUTPUT
s1
s3
1
s1
s5
1
s2
s3
1
s2
s5
1
s3
s2
0
s3
s1
1
s4
s4
0
s4
s5
1
s5
s4
1
s5
s1
0
Algorithm
Example
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1/1
5
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1 = States belong to the same block
when outputs are the same for any input.
While further splitting is possible:
{ k+1 = States belong to the same block
if they were previously in the same block
and their next-states are in the same block
of k for any input.
Example
Example
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minimal nite-state machine
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1 = s1; s2 ; s3; s4 ; s5 :
ff
g f
g f
gg
INPUT
0
1
0
1
0
1
0
1
2 = s1; s2 ; s3 ; s4 ; s5 :
ff
g f
g f
g f
gg
2 = is a partition into equivalence classes:
{ States s1; s2 are equivalent.
f
g
Computational complexity
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Example
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0/1
3
Polynomially-bound algorithm.
0/0
12
1/1
0/1
STATE N-STATE OUTPUT
s12
s3
1
s12
s5
1
s3
s12
0
s3
s12
1
s4
s4
0
s4
s5
1
s5
s4
1
s5
s12
0
0/0
4
1/0
1/1 0/1
1/1
1/1
There can be at most S partition
renements.
j
j
Each renement requires considering each state:
{ Complexity O( S 2).
5
j
j
Actual time may depend upon:
{ Data-structures.
{ Implementation details.
State minimization
for incompletely specied FSMs
State minimization
for incompletely specied FSMs
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Applicable input sequences:
{ All transitions are specied.
Compatible states:
{ Given any applicable input sequence
the corresponding output sequences match.
Compatibility is not an equivalency
relation.
Minimum nite-state machine is not unique.
Implication relations make problem intractable.
Theorem:
{ Two states are compatible i:
they lead to identical outputs
(when both are specied)
and their next-states are compatible
(when both are specied).
Example
Trivial method
for the sake of illustration
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INPUT
0
1
0
1
0
1
0
1
0
1
STATE N-STATE OUTPUT
s1
s3
1
s1
s5
*
s2
s3
*
s2
s5
1
s3
s2
0
s3
s1
1
s4
s4
0
s4
s5
1
s5
s4
1
s5
s1
0
Consider all the possible don't care assignments.
{ n don't care imply
2n completely specied FSMs.
2n solutions.
Example:
{ Replace * by 1.
= s1; s2 ; s3 ; s4 ; s5 :
{ Replace * by 0.
= s1; s5 ; s2; s3; s4 :
ff
g f
ff
g f
g f
g f
gg
gg
Compatibility and implications
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Compatibility and implications
Example
{
{
{
{
{
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Compatible states s1; s2 .
f
g
If s3; s4 are compatible:
f
g
{ then s1; s5 are compatible.
f
Compatible pairs:
s1 ; s2
s1 ; s5
s2 ; s4
s2 ; s3
s3 ; s4
f
g
f
g ( f
g
f
g ( f
g
f
g ( f
g
f
g ( f
g[f
s3; s4
s3; s4
s1; s5
s2; s4
s1; s5
g
g
Incompatible states s2; s5 .
f
g
Incompatible pairs:
{ s2 ; s5 ;
{ s1 ; s4 ;
{ s1 ; s3
s3; s5
s4; s5
f
g
f
g
f
g
f
g
f
g
Compatibility and implications
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A class is maximal:
{ If not subset of another class.
Closure property:
{ A set of classes such that all compatibility
implications are satised.
Maximal compatible classes
A class of compatible states is such that
all state pairs are compatible.
The set of maximal compatibility classes:
{ Has the closure property.
{ May not provide a minimum solution.
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s1 ; s2
f
s1 ; s5
f
g
s2 ; s3 ; s4
f
s3; s4
g ( f
g
s1; s5
g ( f
g
Cover with MCC has cardinality 3.
Formulation of the state minimization
problem
Prime compatible classes
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A class is prime, if not subset of another class
implying the same set or a subset of classes.
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s1 ; s2
f
s1 ; s5
Compute the prime compatibility classes.
f
Select a minimum number of PCC such that:
f
{ all states are covered.
{ all implications are satised.
Binate covering problem.
s3; s4
g ( f
s2 ; s3 ; s4
g
g
s1; s5
g ( f
g
Minimum cover: s1; s5 ; s2; s3; s4 .
ff
g f
Minimum cover has cardinality 2.
State encoding
Heuristic algorithms
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Approximate the covering problem.
Consider all maximal compatibility classes.
{ May not yield minimum.
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Determine a binary encoding of the states:
{ that optimize machine implementation:
{ Preserve closure property.
{ Sacrice minimality.
gg
area.
cycle-time.
Modeling:
{ Two-level circuits.
{ Multiple-level circuits.
Two-level circuit models
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State encoding
for two-level models
Sum of product representation.
{ PLA implementation.
Area:
{ # of products # I/Os.
Symbolic minimization of state table.
Constrained encoding problems.
{ Exact and heuristic methods.
Delay:
{ Twice # of products plus # I/Os.
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Applicable to large nite-state machines .
Note:
{ # products of a minimum implementation.
{ # I/Os depends on encoding length.
State encoding of nite-state machines
Symbolic minimization
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Extension of two-level logic optimization.
Reduce the number of rows of a table, that
can have symbolic elds.
Reduction exploits:
{ Combination of input symbols in the same
eld.
{ Covering of output symbols.
Given a (minimum) state table of a nite-state
machine :
{ nd a consistent encoding of the states
that preserves the cover minimality
with minimum number of bits.
Example
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Primary
Primary
Outputs
COMBINATIONAL
Inputs
Example
Minimum symbolic cover:
CIRCUIT
*
1
0
1
State
REGISTERS
clock
INPUT
0
1
0
1
0
1
0
1
0
1
P-STATE N-STATE OUTPUT
s1
s3
0
s1
s3
0
s2
s3
0
s2
s1
1
s3
s5
0
s3
s4
1
s4
s2
1
s4
s3
0
s5
s2
1
s5
s5
0
001
111
101
100
Covering constraints:
Encoding constraint matrices:
2
A = 10 10 00 11 01
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Encoded cover of combinational component:
1**
101
*00
001
0
1
1
1
0
6 0
B = 664 0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
3
7
7
7
5
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Encoding matrix (one row per state):
2
3
1
1
1
7
6
6 1 0 1 7
6
E = 666 0 0 1 7777
4 1 0 0 5
0 0 0
*
1
0
1
s3
s1
s2
s4
{ s1 and s2 cover s3
{ s5 is covered by all other states.
s1s2s4
s2
s4s5
s3
Multiple-level circuit models
Example
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0
1
1
1
Logic network representation.
{ Logic gate interconnection.
Area:
{ # of literals.
Delay:
{ Critical path length.
Note
{ # literals and CP in a minimum network.
Example
State encoding
for multiple-level models
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Cube-extraction heuristics [Mustang-Devadas].
!
!
{ When two (or more) states have a
transition to the same next-state:
Keep the distance of their encoding short.
!
Extract a large common cube.
Exploit rst stage of logic.
Encoding:
{ s1 000 = a0b0c0.
{ s2 001 = a0b0c.
5-state FSM (3-bits).
{ s1 s3 with input i.
{ s2 s3 with input i0.
Rationale:
!
Transition:
{ ia0b0c0 + i0a0b0c = a0b0(ic + i0c0)
{ 6 literals instead of 8.
Works ne because most FSM logic is shallow.
Diculties
Algorithm
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Examine all state pairs:
{ Complete graph with V = S .
j
j
j
j
Add weight on edges:
{ Model desired code proximity.
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Embed graph in the Boolean space.
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The number of occurrences of common
factors depends on the next-state encoding.
The extraction of common cubes interact with
each other.
Finite-state machine decomposition
Algorithm implementation
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Fanout-oriented algorithm:
{ Based on partition theory.
{ Recently done at symbolic level.
{ Consider present states and outputs.
{ Maximize the size of the most frequent
common cubes.
Fanin-oriented algorithm:
{ Consider next states and inputs.
{ Maximize the frequency of the largest
Dierent topologies:
{ Cascade, parallel, general.
common cubes.
Example
Classic problem.
Recent heuristic algorithms:
{ Factorization [Devadas].
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Summary
COMB. CIRC.
REG
(a)
COMB. CIRC.
COMB. CIRC.
REG
REG
COMB. CIRC.
COMB. CIRC.
REG
REG
(b)
(c)
COMB. CIRC.
REG
REG
(d)
Finite-state machine optimization is
commonly used.
{ Large body of research.
COMB. CIRC.
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State reduction/encoding correlates well to
area minimization.
Performance-oriented methods are still
being researched.
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