Xilinx CPLDs and FPGAs
Module F2-1
CPLDs and FPGAs
XC9500 CPLD
XC4000 FPGA
Spartan FPGA
Spartan II FPGA
Virtex FPGA
XC9500
CPLDs
3
JTAG
Controller
JTAG Port
In-System
Programming Controller
Function
Block 1
I/O
I/O
I/O
I/O
Blocks
I/O
Global
Clocks
Global
Set/Reset
Global
Tri-States
Function
Block 2
FastCONNECT
Switch Matrix
Function
Block 3
3
1
Function
Block 4
2 or 4
5 volt in-system
programmable (ISP)
CPLDs
5 ns pin-to-pin
36 to 288
macrocells
(6400 gates)
Industry’s best pinlocking architecture
10,000
program/erase
cycles
Complete IEEE
1149.1 JTAG
capability
XC9500 Function Block
Global
Clocks
AND
Array
3
Global
Tri-State
2 or 4
Macrocell 1
I/O
Macrocell 18
I/O
ProductTerm
Allocator
36
From
FastCONNECT
To
FastCONNECT
Each function block is like a 36V18 !
XC9500 Product Family
9536
9572
95108
95144
95216
95288
Macrocells
36
72
108
144
216
288
Usable
Gates
800
1600
2400
3200
4800
6400
tPD (ns)
5
7.5
7.5
7.5
10
10
Registers
36
72
108
144
216
288
Max I/O
34
72
108
133
166
192
PC84
TQ100
PQ100
PQ160
PQ100
PQ160
Packages
VQ44
PC44
PC44
PC84
TQ100
PQ100
PQ160
HQ208
BG352
HQ208
BG352
CPLDs and FPGAs
XC9500 CPLD
XC4000 FPGA
Spartan FPGA
Spartan II FPGA
Virtex FPGA
XC4000 Architecture
CLB
Slew
Rate
Control
CLB
Switch
Matrix
D
CLB
Input
Buffer
Programmable
Interconnect
C1 C2 C3 C4
H1 DIN S/R EC
S/R
Control
DIN
G
Func.
Gen.
SD
F'
H'
EC
RD
1
F4
F3
F2
F1
H
Func.
Gen.
F
Func.
Gen.
Y
G'
H'
S/R
Control
DIN
SD
F'
D
G'
Q
H'
1
H'
K
Q
D
G'
F'
Vcc
Output
Buffer
CLB
Q
G4
G3
G2
G1
Q
Passive
Pull-Up,
Pull-Down
EC
RD
X
Configurable
Logic Blocks (CLBs)
D
Delay
I/O Blocks (IOBs)
Pad
XC4000E/X Configurable Logic
Blocks
C1 C2 C3 C4
2 Four-input function
generators (Look Up
Tables)
G4
- 16x1 RAM or
G3
Logic function
G2
G1
2 Registers
- Each can be
configured as Flip
F4
Flop or Latch
F3
- Independent
F2
F1
clock polarity
- Synchronous and
asynchronous
Set/Reset
H1 DIN S/R EC
S/R
Control
DIN
F'
G'
G
Func.
Gen.
SD
EC
RD
1
G'
H'
Y
S/R
Control
DIN
F'
G'
SD
D
Q
XQ
H'
1
H'
K
YQ
H'
H
Func
.Gen.
F
Func.
Gen.
Q
D
F'
EC
RD
X
XC4000 CLB
C2
C1
C3
C4
H1 DIN S/R EC
S/R
Control
G4
G3
G2
G1
DIN
G
Func.
Gen.
SD
F'
Q
D
G'
YQ
H'
EC
RD
1
F4
F3
F2
F1
H
Func
.Gen.
F
Func.
Gen.
G'
Y
H'
S/R
Control
DIN
SD
F'
Q
D
G'
XQ
H'
EC
RD
1
H'
F'
K
X
Look Up Tables
Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB
Look Up Table
4-bit address
Example:
Combinatorial Logic
A B C D
A
B
Z
C
D
 Capacity is limited by number of
inputs, not complexity
 Choose to use each function
generator as 4 input logic (LUT) or
as high speed sync.dual port
WE
RAM
G4
G3
G2
G1
G
Func.
Gen.
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Z
0
0
0
1
1
1
. . .
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
4
(2 )
2
= 64K !
XC4000X I/O Block Diagram
Shaded areas are not included in XC4000E family.
Xilinx FPGA Routing
1) Fast Direct Interconnect - CLB to CLB
2) General Purpose Interconnect - Uses switch matrix
3) Long Lines
Segmented across
chip
Global clocks, lowest
skew
2 Tri-states per CLB
for busses
Other routing types in
CPLDs and XC6200
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
CLB
Other FPGA Resources
Tri-state buffers for busses (BUFT’s)
Global clock & high speed buffers
(BUFG’s)
Wide Decoders (DECODEx)
Internal Oscillator (OSC4)
Global Reset to all Flip-Flops, Latches
(STARTUP)
CLB special resources
Fast Carry logic built into CLBs
Synchronous Dual Port RAM
Boundary Scan
What’s Really In that Chip?
Programmable Interconnect Points, PIPs (White)
Switch
Matrix
Routed Wires (Blue)
Direct
Interconnect
(Green)
CLB
(Red)
Long Lines
(Purple)
Xilinx XC4000E FPGAs
CPLDs and FPGAs
XC9500 CPLD
XC4000 FPGA
Spartan FPGA
Spartan II FPGA
Virtex FPGA
Xilinx Spartan FPGAs
CPLDs and FPGAs
XC9500 CPLD
XC4000 FPGA
Spartan FPGA
Spartan II FPGA
Virtex FPGA
Xilinx Spartan-II FPGAs
Block RAM
Delay-Locked Loop
Phase-Locked Loop
CPLDs and FPGAs
XC9500 CPLD
XC4000 FPGA
Spartan FPGA
Spartan II FPGA
Virtex FPGA
Virtex FPGAs
Virtex-II FPGAs
Virtex-II Pro FPGAs