VLSI TESTING PROJECT
Dominance Fault Collapsing
Anandshankar Mudlapur
Arun Balaji Kannan
Muthu Balaji Ramkumar
Muthu Balan Varadharajaperumal
Dominance Fault Collapsing
1
Dominance collapsed faults for an AND gate
SA0,SA1
A
SA0,SA1
A
SA0,SA1C
SA0,SA1
B
C
B
Un-collapsed faults
SA1
Dominance collapsed faults
Faults
Test Vectors
“AB”
A-SA0
11
A-SA1
01
B-SA0
11
B-SA1
10
C-SA0
11
C-SA1
00, 01, 10
Compulsory
Fault
Collapsed
Faults
A-SA0
B-SA0,
C-SA0
A-SA1
C-SA1
B-SA1
C-SA1
Dominance Fault Collapsing
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Dominant faults modeled on different gates and fan-outs
A
B
A
Compulsory Faults
Optional Faults
A-SA1, B-SA1
A-SA0 or B-SA0
A-SA0, B-SA0
A-SA1 or B-SA1
C
A-SA1, B-SA1
A-SA0 or B-SA0
C
A-SA0, B-SA0
A-SA1 or B-SA1
C
A-SA0, A-SA1
-
C
A-SA0, A-SA1, B-SA0,
B-SA1, C-SA0, C-SA1
-
C
C
B
A
B
A
B
A
A
B
A1
A
A2
A
A
A-SA0, A-SA1,
A1-SA0, A1-SA1,
A2-SA0, A2-SA1
-
A-SA0, A-SA1
-
Dominance Fault Collapsing
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Algorithm

Necessary information is read from the bench file

Parse the circuit from input to output or vice-versa

Check if the node is of type XOR and assign the compulsory faults ( SA0
and SA1) at the output.
Repeat for all nodes:


Check if node is an input and if fan-outs are greater than 2 assign both
faults for the node.
All the inputs of the gates are scanned and checked for the node type
o If fan-out of the input >= 2, assign compulsory fault
o Else if gate is BUF or NOT and input is PI assign both faults
o Else if PI, assign compulsory fault and note input #
o Else if gate output, set a FLAG
Dominance Fault Collapsing
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Algorithm Continued…


Check if FLAG is unchanged and if no primary inputs are encountered; assign
the optional fault to the last input
Else if FLAG is unchanged; assign the optional fault to the PI
End Loop

If PO has fan-outs; both faults are assigned

The result obtained is saved!
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
J
A
L
B
C
H
D
E
M
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
J
A
L
B
C
H
D
E
0,1
M
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
A
0,1
J
L
B
C
H
D
E
0,1
M
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
H
D
E
0,1
M
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
D
E
H
1
0,1
M
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
D
E
H
1
0,1 1
M
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
D
E
H
0,1
0,1 1
M
F
K
G
Dominance Fault Collapsing
6
Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
D
E
H
0,1
0,1 1
M
1
F
K
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
D
E
H
0,1
0,1 1
M
1
F
K
1
G
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
B
1
C
D
E
H
0,1
0,1 1
M
1
F
K
1
G 1
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
1
B
1
C
D
E
H
0,1
0,1 1
M
1
F
K
1
G 1
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
L
1
B
1
C
D
E
H
0,1
0,1 1
1
M
1
F
K
1
G 1
Dominance Fault Collapsing
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Example of Dominance Fault collapsing using the above algorithm
0,1
A
J
0,1
L
1
B
1
C
D
E
H
0,1
0,1 1
1
M
1
F
K
1
G 1
Dominance Fault Collapsing
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Results
Benchmark Circuits
C17
74181
Total Faults
(HITEC GENERATED)
46
500
Collapsing
Method
Equivalence
Dominance
Benchmark
circuit
HITEC
Our
Program
C17
22
16
74181
(XOR)
237
208
74181
(NAND
MODEL for
XOR)
301
248
Dominance Fault Collapsing
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Conclusion
As a conclusion,
 Results may coincidentally match!
 A Double check on the results : always
advisable
 Plan what you do, do what you plan and
record what you have accomplished!
Dominance Fault Collapsing
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