Pocket Guide to Processors for DSP
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Last updated November 2005
CHIPS
BDTImark
Vendor
Analog
Devices
Data
Width
BDTImem
Core
Clock
Total On-Chip
2000™
Mark
Speed BDTIsimMark
Memory, Bytes
[1]
2000™ [3]
2000™ [2]
ADSP-218x
Fixed
point
16 bits
80
MHz
240
65
ADSP-219x
Fixed
point
16 bits
160
MHz
410
63
Family
Floating,
Fixed,
or Both
ADSP-2126x
(SHARC)
Floating
200
32/40 bits
point
MHz
ADSP-213xx
(SHARC)
Floating
400
32/40 bits
point
MHz
1090
2050
34
34
Unit Price
[4]
Notes
16 K–208 K
$6–26
Many family
members w/ assorted
peripherals
16 K–128 K
$11–26
Enhanced version of
the ADSP-218x
$10–15
Features SIMD,
strong
multiprocessor
support
$17–35
SHARC with a
lengthened pipeline
for higher clock
speeds
512 K–768 K
896 K–1024 K
ADSP-BF5xx
(Blackfin)
Fixed
point
16 bits
750
MHz
4190 [5,6]
72 [5,6]
84 K–328 K
$5–60
Dual-MAC DSP
with variable speed
and voltage
$47–205
4-way VLIW with
SIMD capabilities;
uses eDRAM
ADSP-TS20x
(TigerSHARC)
Both
8/16/32/40 600
bits
MHz
DSP563xx
Fixed
point
24 bits
275
MHz
820
50
24 K–648 K
$4–47
Many audio-oriented
parts; binarycompatible with
’560xx
DSP56F8xx
(56800)
Fixed
point
16 bits
80
MHz
[7]
110
78
28 K–152 K
$3–10
Contains many
microcontroller-like
features
DSP5685x/
56F8xxx
(56800E)
Fixed
point
16 bits
120
MHz
340
79
20 K–612 K
$3–18
Enhanced version of
the ’568xx
MSC71xx
(SC1400)
Fixed
point
16 bits
300
MHz
$13–35
Based on SC1400
licensable core (see
below)
MSC81xx
(SC140)
Fixed
point
16 bits
500
MHz
5610 [5]
67 [5]
514 K–1440 K
$77–205
Based on SC1400compatible core;
most chips use 4
cores
LSI Logic
LSI40x
(ZSP400)
Fixed
point
16/32 bits
200
MHz
940
74
96 K–252 K
$4–9
Based on ZSP400
licensable core (see
below)
Microchip
dsPIC3xF
Fixed
point
16 bits
40
MHz
130
78
12.5 K–286 K
$4–14
Hybrid
microcontroller/DSP
Freescale
6400 [6]
3370
52 [6]
67
512 K–3 M
88 K–472 K
NEC
Renesas
μPD77050
(SPXK5)
Fixed
point
SH76xx
(SH2-DSP)
SH772x
(SH3-DSP)
16 bits
250
MHz
Fixed
point
16 bits
62.5
MHz
170
70
Fixed
point
16 bits
200
MHz
490
70
1770
65
$14
Dual-MAC DSP
with variable speed
and voltage
12 K–20 K
$13–15
Hybrid
DSP/microprocessor
based on SH2-DSP
32 K–48 K
$17–25
Hybrid
DSP/microprocessor
based on SH3-DSP
400 K
SH77xxx
(SH-4)
Both
16/32 bits
400
MHz
1250
50
48 K–64 K
$21–35
Superscalar
microprocessor with
3D geometry
instructions
TMS320C24x/
F24x
Fixed
point
16 bits
40
MHz
n/a
n/a
13 K–69 K
$2–9
Hybrid
microcontroller/DSP
TMS320C28x/
F28x
Fixed
point
32 bits
150
MHz
n/a
n/a
40 K–294 K
$6–16
Hybrid
microcontroller/DSP;
assembly-compatible
w/ ’C24x
Fixed
point
16 bits
160
MHz
500 [5]
64 [5]
24 K–520 K
$4–54
Many specialized
instructions
TMS320C55x
Fixed
point
16 bits
300
MHz
1460
75
80 K–376 K
$4–18
Dual-issue, dualMAC DSP;
assembly-compatible
w/ ’C54x
TMS320C64x/
DM64x
Fixed
point
8/16 bits
1
GHz
9130
53
160 K–1056 K
$18–219
Texas
TMS320C54x
Instruments
Adds quad-MAC
capabilities and
specialized
operations to 'C62x
TMS320C64x+
Fixed
point
8/16 bits
1
GHz
10980
60
2112 K
$179–259
Adds 8-MAC
capabilities and
specialized
operations to 'C64x
TMS320C67x
Floating
point
32 bits
300
MHz
1470
35
16 K–128 K
$16–110
Floating point
version of ’C62x
$10–20
Adds registers and
audio-oriented
instructions to the
’C67x
TMS320C67x+
Floating
point
32 bits
300
MHz
n/a
n/a
160 K–288 K
CORES
Licensor
Family
Floating,
Fixed, or
Both
Data
Width
Core
Clock
Speed
[1,8]
Total Core
BDTImark2000™
Die area
BDTImemMark2000™
BDTIsimMark2000™
Memory
[3]
[8]
[2]
Space, Bytes
Notes
ARC 600/
16/32 bits
Fixed point
ARC XY
[9]
180
MHz
[10]
n/a
n/a
4G
0.77 mm² Customizable core with
[10]
optional DSP features
ARC 700/
16/32 bits
Fixed point
ARC XY
[9]
265
MHz
[10]
n/a
n/a
4G
1.1 mm² Longer pipeline enables
[10]
higher clock rate
ARC
ARM7
Fixed point
32 bits
145
MHz
150
57
4G
0.28 mm²
Widely licensed 32-bit
microprocessor core
ARM9
Fixed point
32 bits
265
MHz
330
74
4G
n/a
Adds separate bus for
data access, deeper
ARM
pipeline to ARM7
Fixed point 16/32 bits
265
MHz
ARM1136 Fixed point 16/32 bits
330
MHz
1160
ARM9E
CEVATeakLite
CEVA
LSI
Logic
550
ARM9 enhanced with
single-cycle MAC unit
4G
1.7 mm²
72
4G
Adds SIMD, load/store
2.9 mm² unit, branch prediction,
deeper pipeline
72
Fixed point
16 bits
170
MHz
n/a
n/a
256 K
0.4 mm²
Single-MAC, singleissue DSP core
CEVAFixed point
TeakLite II
16 bits
200
MHz
n/a
n/a
4M
0.5 mm²
Faster version of
CEVA-TeakLite
CEVA-Teak Fixed point
16 bits
150
MHz
n/a
n/a
8M
0.9 mm² Dual-MAC DSP core
CEVAX1620
Fixed point 8/16 bits
330
MHz
2660
67
4G
2.6 mm²
8-way VLIW, dualMAC DSP core
ZSPneo
Fixed point 16/32 bits
165
MHz
n/a
n/a
256 K
0.45 mm²
Single-MAC, scalar
variant of the ZSP400
ZSP200
Fixed point 16/32 bits
165
MHz
n/a
n/a
256 K
Single-MAC, 2-way
0.7 mm² superscalar variant of
the ZSP400
ZSP400
Fixed point 16/32 bits
165
MHz
780
74
256 K
1.3 mm²
ZSP500
Fixed point 16/32 bits
205
MHz
1620
68
64 M
Second-generation
2.2 mm² ZSP; dual-MAC, 4-way
superscalar
ZSP540
Fixed point 16/32 bits
200
MHz
n/a
n/a
64 M
2.7 mm²
Dual-MAC, 4-way
superscalar DSP core
Quad-MAC, 4-way
variant of the ZSP500
Philips
ZSP600
Fixed point 16/32 bits
175
MHz
n/a
n/a
64 M
3.1 mm²
CoolFlux
DSP
Fixed point
24 bits
175
MHz
n/a
n/a
640 K
Dual-MAC core targets
0.34 mm² low-power audio
applications
SC1200
Fixed point
16 bits
200
MHz
1580
69
4G
1.9 mm²
16 bits
185
MHz
2080
67
4G
Synthesizable version
2.3 mm² of quad-MAC, 6-issue
SC140
210
MHz
[11]
3490 [11]
69 [11]
4G
VLIW-based
3.7 mm²
customizable core; with
[11]
optional DSP features
StarCore
SC1400
Tensilica
Fixed point
Xtensa LX/
Fixed point 18 bits [9]
Vectra LX
Quad-MAC, 6-way
variant of the ZSP500
Dual-MAC, 4-issue
variant of the SC1400
NOTES:
[1] Chips: clock speed for fastest family member. Cores: worst-case clock speed.
[2] The BDTImark2000 and BDTIsimMark2000 provide summary measures of DSP speed; for both scores, higher is faster. Both scores are calculated with the
same formula, but BDTIsimMark2000 scores may use projected clock speeds. BDTImark2000 scores are shown in bold and BDTIsimMark2000 scores in
italic. See www.BDTI.com/benchmarks.html for more information and scores.
[3] The BDTImemMark provides a summary measure of memory use in signal processing applications; higher is better. See www.BDTI.com/benchmarks.html
for more information and scores.
[4] Unit prices based on vendors’ quotations for 10,000-unit orders. Prices are as of the third quarter of 2005.
[5] Score for one core. Some family members contain multiple cores. Details available from BDTI.
[6] Score does not apply to some family members, which use slightly different architectures. Details available from BDTI.
[7] The DSP56F8xx requires two clock cycles per instruction cycle.
[8] Philips CoolFlux DSP data is for a 0.13 µm Philips process. All other core data is for the TSMC CL013G process and ARM Artisan SAGE-X library.
[9] Native multiplier width(s). Users may add custom instructions that support other data widths.
[10] Assumes use of optional DSP extensions but no other optional features.
[11] Assumes use of 12 custom instructions that expand the area of the core by 16%. Licensees may require greater or lesser degrees of
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2107 Dwight Way, Second Floor
Berkeley, CA 94704 U.S.A.
Tel: +1 (510) 665-1600 Fax: +1 (510) 665-1680
[email protected]
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