ECE232: Hardware Organization and Design
Part 10: Control Design
http://www.ecs.umass.edu/ece/ece232/
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB
Datapath With Control
ECE232: MIPS Control 2
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
R-Format Instruction: add $t1, $t2, $t3
Memto- Reg Mem Mem
Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
R-format
1
0
0
1
0
0
0
1
0
ECE232: MIPS Control 3
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Load Instruction
Memto- Reg Mem Mem
Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
lw
0
1
1
1
1
0
0
0
0
ECE232: MIPS Control 4
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Branch-on-Equal Instruction
Memto- Reg Mem Mem
Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
beq
x
0
x
0
0
0
1
0
1
ECE232: MIPS Control 5
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Simple combinational logic
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg
Write
1
1
0
0
Mem
Read
0
1
0
0
Mem
Write
0
0
1
0
Branch
0
0
0
1
ALUOp1
1
0
0
0
ALUp0
0
0
0
1
In p u ts
O p5
O p4
O p3
O p2
O p1
O p0
O u tp u ts
R - fo r m a t
Iw
sw
be q
R e gD st
A LU S rc
M e m to R e g
R e g W rite
M emRead
M e m W rite
B ra n ch
A LU O p1
A LU O pO
ECE232: MIPS Control 6
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Single-Cycle Machine: Appraisal
 All instructions complete in one clock cycle (CPI = 1)
 Some instructions take more steps than others
• lw is most expensive (5 steps, vs. 4 for R-type and sw, 3
for beq)
 Clock cycle must cover longest instruction  inefficient
• suppose mult is added?
• 32-shift/add steps  would delay every other instruction
ECE232: MIPS Control 7
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Cycle time and speedup computation
 Assume:
• 2ns for instruction/data memory
• 1ns for decode/register read
• 2ns for ALU and
• 1ns for register write
 Single-cycle datapath clock period = 8ns
 Assume an instruction mix of 24% loads, 12% stores, 44%
R-format, 18% branches, and 2% jumps
 Assuming a variable-cycle datapath, average clock period =
8*0.24+7*0.12+6*0.44+5*0.18+3*0.02=6.36 ns
 Possible Speed-up = 1.26
ECE232: MIPS Control 8
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Multicycle Implementation (MIPS-lite v.2)
 Want more efficient implementation
 Each step will take one clock cycle (not each instruction)
[CPI > 1]
• shorter clock cycle: cycle time constrained by longest
step, not longest instruction
• simpler instructions take fewer cycles
• higher overall performance
 More complex control: finite state machine
 Versatile (can extend for new instructions: swap, mult-add
etc.)
ECE232: MIPS Control 9
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Clocking: single-cycle vs. multi-cycle
Single-cycle Implementation
clock
waste
waste
beq $t0,$t1,L
add $t0,$t1,$t2
Multicycle Implementation
clock
add $t0,$t1,$t2
beq $t0,$t1,L
Multicycle Implementation: less waste=higher performance
ECE232: MIPS Control 10
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
How fast can we run the clock?
 Depends on how much we want to be done per clock cycle
• Can do: several “inexpensive” datapath operations per
clock
• simple gates (AND, OR, …)
• single datapath registers (PC)
• sign extender, left shifter, multiplexor
• OR: exactly one “expensive” datapath operation per clock
• ALU operation
• Register File access (2 reads, or 1 write)
• Memory access (read or write)
ECE232: MIPS Control 11
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
MIPS-lite
Multicycle Version
Multicycle Datapath (overview)
P
C
Address
Memory
Instruction
Register
Read
Reg2
Instruction
or Data
Data
Read
Reg1
Read
data 1
A
Registers
Memory
Data
Register
Write
Reg
Read
data 2
A
L
U
ALUOut
B
Data
• One ALU
(no extra adders)
• One Memory (no separate IMem, DMem)
• New Temporary Registers (“clocked”/require clock input)
ECE232: MIPS Control 12
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Multicycle Implementation
 Datapath changes
• one memory: both instructions and data (because can
access on separate steps)
• one ALU (eliminate extra adders)
• extra “invisible” registers to capture intermediate (perstep) datapath results
 Controller changes
• controller must fire control lines in correct sequence and
correct time
 controller must remember current execution step,
advance to next step
ECE232: MIPS Control 13
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Datapath + Control Points
RegWrite
MemRead IRWrite
RegDst
IorD MemWrite
P
C
M
u Address
x
Mem
Read
Data
Write
Data
PCSrc
ALUSrcA
PCWriteCond
25:21
Read
Reg1
Read
A
Read data1
20:16
Reg2
M
Write Read
u
B
15:0 15:1
data2
Reg
1 x
IR
Regs
M Write
M
u Data
D
x
R
Sgn
<<
Ext2
end
(funct)
5:0
MemtoReg
ECE232: MIPS Control 14
PCWrite
M
u
x
z
A
L
U
0
4 1M
2u
3x
M
u
x
ALUOut
3
ALU
Control
2
2
ALUSrcB
ALUOp
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
FSM diagram for multi-cycle machine
start new
instruction
state 0
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 1
ALUOp = 0
PCWrite
PCSrc = 0
cycle
1
cycle
2
1
ALUSrcA = 0
ALUSrcB = 3
ALUOp = 0
8
cycle
3
6
ALUSrcA = 1
ALUSrcB = 2
ALUOp = 0
Memory
Access
ECE232: MIPS Control 15
2
ALUSrcA = 1
ALUSrcB = 0
ALUOp =2
R-format
execution
ALUSrcA = 1
ALUSrcB = 0
ALUOp =1
PCWriteCond
PCSrc = 1
Branch
Completion
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
FSM controller: execution cycles 3-5
from state 6
from state 2
sw
lw
3
cycle
4
7
5
MemRead
IorD = 1
memory
access
(step 4)
to state 0
MemWrite
IorD = 1
memory
access
(step 4)
RegDst = 1
RegWrite
MemtoReg = 0
R-format
completion
(step 4)
4
cycle
5
RegDst = 0
RegWrite
MemtoReg = 1
write-back (step 5)
ECE232: MIPS Control 16
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren
Cycle 1
RegWrite
MemRead IRWrite
RegDst
IorD MemWrite
P
C
M
u Address
x
Write
Data
20:16
15:0
IR
M
D
R
15:
11
PCWriteM
Cond
u
x
Read
Read data1
Reg2
M
Read
u Writedata2
x Reg
M Write
u Data
x
ECE232: MIPS Control 17
A
B
Regs
Sgn
Extend
MemtoReg
PCSrc
ALUSrcA
Read
Reg1
25:21
Mem
Read
Data
PCWrite
M
u
x
z
A
L
U
0
4 1M
2u
3x
ALUOut
3
ALU
Control
<<
2
(funct)
5:0
Cycle 1
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 1
ALUOp = 0
PCWrite
PCSrc = 0
2
2
ALUSrcB
ALUOp
Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass
Koren