VeriLogger Pro is a new type of Verilog simulation environment that combines all the
features of a traditional Verilog simulator with the most powerful graphical test vector
generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform
true bottom-up testing of every model in your design, a critical step often skipped in the
race to market.
Verilog Simulator with Graphical Test Vector Generation
VeriLogger Pro, by SynaptiCAD is a complete design and verification environment for
ASIC and FPGA designers. It contains a new type of Verilog simulation environment
that combines all the features of a traditional Verilog simulator with the most powerful
graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro
that you can perform true bottom-up testing of every model in your design, a critical
step often skipped in the race to market. Test vectors can be imported or exported from
HP logic analyzers, pattern generators, and 3rd party VHDL, Verilog, and SPICE
simulators for reuse. Simulation features include waveform viewing, optimized gatelevel simulation, single-step debugging, point-and-click breakpoints, hierarchical
browser for project management, and batch execution.
Customer Feedback



"A great simulator at a very accessible price..." Gill Romero, Principal
Consultant, ASIC Alliance
"The timing diagram editor included with Verilogger helped me design the
synchronizing circuit quickly..." Sam Mitchum, Philips Semiconductors
"I really love VeriLogger!... " Mike Kentley, High Desert Design Center
Watch an Animated Tutorial of Verilogger Pro

Basic VeriLogger Pro Animated Tutorial
Technical Details






VeriLogger Pro Features
Graphical Stimulus Generation Features
Interactive Simulation Features
Batch Mode Operation
Interactive Screen Shot
Download VeriLogger Pro literature in Acrobat format
Evaluate and Purchase VeriLogger:




Pricing
Download an evaluation version of VeriLogger Pro
VeriLogger Pro FAQ
Features List
Complete ASIC and FPGA design Environment
In a typical design of a large ASIC, each contributing engineer can use a VeriLogger to
develop and simulate their portion of the chip. After each portion has been synthesized
and checked, the entire integrated design can be rapidly simulated and verified using
VeriLogger with its optimized gate level simulation engine activated. VeriLogger
interfaces to synthesis tools, place-and-route tools, and all vendor Verilog libraries.
VeriLogger supports design flows using Actel, Altera, Lattice, Lucent, Quicklogic, Vantis
, and Xilinx devices including full timing verification.
Graphical Test Bench Generation
VeriLogger can automatically generate test bench code for your design models. Using
the built-in timing diagram editor, just draw the stimulus waveforms and VeriLogger will
write the test bench and simulate it with your design models. VeriLogger also includes
an instant-feedback simulation mode in which any change to the design code or the
waveform stimulus vectors results in an automatic re-simulation. This mode is
especially useful for quickly verifying the functionality of small design blocks, making it
possible to perform true unit-level testing of designs.
Cut your Design Costs by a Factor of 10
If you've wanted to move up to the latest design methodologies, but have hesitated
because of the high entry costs, VeriLogger is your answer. If you've already moved to
Verilog, but haven't been able to afford to equip all the members of your team with their
own simulators, VeriLogger is your answer too. VeriLogger is 100% compatible with
Verilog-XL and integrates seamlessly into an XL environment.
Got a question about VeriLogger Pro and HDLs?
Post your question on the newsgroup comp.lang.verilog and it will be answered by our
technical support staff (the newsgroup is checked at least once a day). You can always
call 800-804-7073 to have any questions answered directly.
Direct Sales Line: 800-804-7073 | Phone: 540-953-3390 | Email: [email protected] | Fax: 540-953-3078
Home | Whats New | Search | Downloads | Pricing | TestBencher
VeriLogger | WaveFormer | DataSheet | TimingDiagrammer | Tech Papers | App Notes
Tutorials | EDA Links | Tektronix | Agilent | About SynaptiCAD | Employment | Distributors
COPYRIGHT 2001, SYNAPTICAD INC., ALL RIGHTS RESERVED.
Timing Diagrammer Pro, WaveFormer Pro, TestBencher Pro, VeriLogger Pro, DataSheet Pro and SynaptiCAD are trademarks of
SynaptiCAD, Inc.
All other marks are trademarks of their respective owners.
vhdl verilog SPICE Pspice timing analysis test bench generation ABEL Minc viewlogic vhdl verilog vhdl verilog vhdl verilog vhdl verilog
Customer Feedback
Below, some customers share their experiences with SynaptiCAD's products. If you
would like to share your own experience using our products, send them to
[email protected]..
TestBencher Pro has been invaluable at all levels of our ASIC design. Its flexibility
allows us to create testbenches for simple submodules within minutes, or highly
complex transaction based models for modules and module groups. Synapticad has
provided outstanding customer service and product training, and has in my opinion
delievered the highest value per dollar of any tool we have purchased to date. The
waveform and datasheet generator save many painful hours of sketching wafeform
timing by hand.
Jay Abel
VP Product Development, Shera International
Dear SynaptiCAD,
As a customer of Synapticad products for the past three years, I want to give you some
feedback on your Verilog simulator and test bench generation tools.
I have used the Verilogger product on three different ASIC designs for Hewlett-Packard
Company and have been successful in meeting a demanding schedule with fully
functional parts. I contribute my high level of performance and success to the use of
your Verilogger product. The integrated editor, simulator, interactive debugger and
waveform viewer has provided me with tools to efficiently design and test various
hardware blocks in an ASIC. I have been able to perform initial verification of various
Verilog hardware blocks using the waveform drawing capabilities of your product where
the test bench is produced automatically from the waveforms. This has saved me
considerable time during the development process since I can perform an initial
verification without writing a single line of Verilog test bench code. I can also use the
various waveform files for documentation of the ASIC design.
After I have performed the initial verification, I spend a considerable amount of time in
manually generating a comprehensive Verilog test bench for the ASIC design with
associated Verilog models. I have recently purchased the Testbencher product which
adds test bench generation capability to the integrated environment described above. I
have been able to generate Verilog code models for various peripherals connected to
an ASIC under test in record time without writing much Verilog code. I plan on using
Testbencher for generating comprehensive test benches that I had previously
generated manually and were prone to many errors. I can generate the various
waveform files for the various models connected to the chip-under test with selfchecking capability (samples) using the integrated waveform drawing tool and
Testbencher generates the Verilog test bench.
Testbencher is the most complete and comprehensive Verilog design tool that I have
ever used.
Synapticad has an excellent customer service department. I have communicated
various issues with the Synapticad toolset and have received a response at all times
within 24 hours. I appreciate the support and flexibility that Synapticad has provided to
me during my short development schedules.
George Lysy
Hewlett-Packard Company
"I'm impressed with SynaptiCAD, they have a great simulator at a very accessible price.
I found it to be 100% Cadence Verilog-XL compatible. My test case simulated the same
RTL code from a big FPGA (Xilinx Virtes-300/600/1000 and an Altera 10k150) in
Verilog XL and in VeriLogger with no problems. Even on a machine with only 128M of
RAM, VeriLogger performed well. The SynaptiCAD staff was very quick to answer any
question and I have always found them to be very responsive and helpful."
Gill Romero
Principal Consultant, ASIC Alliance Corp.
"Hi Gary,
Just a quick note to let you know how helpful I have found SynaptiCAD's Verilogger.
I am currently working on a design which involves two clocks, asynchronous with
respect to each other. The timing diagram editor included with Verilogger helped me
design the synchronizing circuit quickly. I started with a new diagram, added the two
clocks and the synchronizing signal. Then I started adding / modifying signals until I
reached a design that looked good.
Having the ability to draw new signals and specify their behavior with equations then
to see Verilogger's timing diagram editor correctly simulate the signals really makes the
detail design work go quickly. It means I no longer have to waste a lot of time sketching
stuff out on the whiteboard, opening an editor, writing the code, creating a test bench
and pulling it into the simulator to verify correct operation. Verilogger has all this
functionality built in. The point-and-click style for creating signals is extremely easy to
learn and use. And it is easy to assign an equation to a signal -- right click to open the
properties for the signal and the equation box is right there.
Also thanks for pointing out how easy it to specify and name a group of signals I
want to watch as a View into a particular timing diagram. I have a few groups specified
(the afore-mentioned clocks) and it only takes two clicks to switch back and forth among
them. That really makes it easy to check out parts of the design and make sure none of
my new "fixes" have broken any of the other code. Thanks again"
Sam Mitchum
Philips Semiconductors
"Hi Gary,
By the way, I really love VeriLogger! I'm using the command line version in a
makefile to automate all my sim runs for the current project, and then use the GUI for
debug. This will be the first ASIC I've done entirely with VeriLogger and the price is
great!"
Mike Kentley
High Desert Design Center
"Hi Gary,
I've been really happy with your phone support. A few weeks ago I was working
from home and had a problem working in Waveformer. It was the day after I spoke with
you on the phone and I thought I had remembered you mentioning that you were going
to be at work on Saturday, so I went ahead and called. I don't remember the name of
who answered, but your phones where being forwarded to somebody at home. And he
got me the help that I needed. On Saturday. Awesome! "
Jim Means
L3 Communications
"Waveformer Pro has been invaluable to me for working thru design ideas as well as
documenting the design implementation. One of my recent designs, a Crossbar Switch
Arbiter implemented in an Altera CPLD, was a heavily pipelined architecture using time
division multiplexing. Waveformer Pro was used to initially brainstorm device operation
and to document how each pipe element worked and would feed the next element in
the pipe. Waveformer Pro has also been used to document system timing
considerations, which have formed the backbone of a 64Gbit router design. All timing
considerations have been included in a waveform diagram and timing spreadsheet
indicating how all router line cards must implement the back-end design. This diagram
will become the basis of our system design documentation. Waveformer Pro has been
easy to use and exactly the tool that today's design engineer needs to include as part of
one's design methodology."
Andrew M. Norton
Norton Engineering Consultants
"The combination of WaveFormer Pro and HP logic analyzers lets designers use
captured waveforms as stimulus vectors to drive the simulation of a circuit. This
capability allows fast debugging and should help our customers bring their products to
market sooner.”

Customer Success at IBM!
Patrick J. Byrne, General Manager
Hewlett-Packard Colorado Springs Division
As a group of ASIC design engineers we often deal with chip, interface and system
level timings. Powerful simulation tools are used to verify if the timing design goals were
achieved. Nevertheless, the planning of the timing must be done with pencil and paper.
Documenting the complex waveforms with the built in drawing tools of a standard word
processing software is another tedious task. And who will repeat that lengthy procedure
when a design modification requires a slightly changed timing?
The WaveFormer is a valuable tool that bans paper and pencil from the desk when
planning complex timing diagrams, and it is not more difficult to use. Entering and
editing signals and timing parameters is quickly learned by doing. Worth mentioning is
the fact how fast you handled a request regarding a bug in WaveFormer Pro 5.1, ...
nobody is perfect, but it would not matter if everybody would respond as fast as you did.
H. Thielemann, SIEMENS AG, Germany
Mobile Radio Hardware Development
Just thought I would drop you a note to let you know Panametrics Engineering loves
WaveFormer Pro for designing Viewlogic Simulation stimulus...
Steve Besser
Panametrics Engineering
I had to make a decision a year ago whether to go with WaveFormer or Timing
Designer [by Chronology Corporation]. I am glad I picked WaveFormer! You have done
a great job adding new features, keep up the good work.
One request I would like to make: when entering timing relationships, it would be very
nice to just double click on the timing constraint, and a dialog box pops up with a link
directly into the timing database, so that I can quickly enter a library timing parameter.
This was handy in Timing Designer, but it isn't enough to switch back ;-)
Follow up email, received 10 minutes later the same day
Sorry about that, I guess I didn't have time to check over all the new features in this
release. It has a much better way of entering libraried timing parameters via the pop up
dialog box (just didn't see it)!
Stephen Noftall
Level Control Systems
Subject: Many Kudos...
Well, I recieved WaveFormer this morning around 10:30am and its around 12:30 now.
In 2 hours I feel I've gotten a pretty good feeling for the program. Excellent tutorial. It
shows how to use the software in a real situation but doesn't belabor the trival stuff.
From the doc notes, it seems like you've been adding significant functionality with each
new release, yet you've been able to keep the program easy to learn. Given my several
previous experiences trying to get up to speed on CAD programs in a day or so, you
have done an incredible job. Its easy enough to learn and use that I am already
_designing_ system timing in the program, rather than just entering and checking my
hand-written hen scratches. WOW!
Also, I didn't realize it when I ordered the sotware, but thanks for not having a dongle. I
hate having to carry those darn things around with my laptop if I take work home. I'm
always scared that someone will steal it or I'll lose it.
Well, I got to get back to the grindstone. Oh, by the way, the reason that I'm now
designing on the system is that after entering about a dozen waveforms, etc in a
complicated dram controller, I found subtle timing error that now I have to fix. I suspect
that finding this problem early probably just paid for the tool.
C. Bolton
Bolton Engineering Inc
Subject: WaveFormer Testimonial
I've been using the Waveformer since 1994 and find it to be an indispensible tool in
both design analysis and synthesis. I've applied the Waveformer to optimize both
performance and cost in product upgrades. I use it to synthesize new designs as well. It
allows me to define my timing constraints which help to determine what components I
will use. Once chosen, I can re-simulate and use the timing diagrams as a reference for
simulation waveforms. I can freely investigate scenarios such as matching memory to
processor speeds without the need for schematics or behavioral models. The timing
diagrams are used and re-used from upgrade to upgrade and from design to new
design. The Waveformer is an important tool which bridges the gap between the worlds
of analysis and synthesis.
Ralf Chlipalski
Senior Design Engineer, Gandalf Canada Ltd.
WaveFormer's instant feedback environment takes the headache out of system level
timing. No digital designer should be without it!
Mark Knecht
Virtual Chips (Phoenix Technologies)
Direct Sales Line: 800-804-7073 | Phone: 540-953-3390 | Email: [email protected] | Fax: 540-953-3078
Home | Whats New | Search | Downloads | Pricing | TestBencher
VeriLogger | WaveFormer | DataSheet | TimingDiagrammer | Tech Papers | App Notes
Tutorials | EDA Links | Tektronix | Agilent | About SynaptiCAD | Employment | Distributors
COPYRIGHT 2001, SYNAPTICAD INC., ALL RIGHTS RESERVED.
Timing Diagrammer Pro, WaveFormer Pro, TestBencher Pro, VeriLogger Pro, DataSheet Pro and SynaptiCAD are trademarks of
SynaptiCAD, Inc.
All other marks are trademarks of their respective owners.
vhdl verilog SPICE Pspice timing analysis test bench generation ABEL Minc viewlogic vhdl verilog vhdl verilog vhdl verilog vhdl verilog
Customer Feedback
Below, some customers share their experiences with
SynaptiCAD's products. If you would like to share your own
experience using our products, send them to
[email protected]..
TestBencher Pro has been invaluable at all levels of our
ASIC design. Its flexibility allows us to create testbenches for
simple submodules within minutes, or highly complex
transaction based models for modules and module groups.
Synapticad has provided outstanding customer service and
product training, and has in my opinion delievered the
highest value per dollar of any tool we have purchased to
date. The waveform and datasheet generator save many
painful hours of sketching wafeform timing by hand.
Jay Abel
VP Product Development, Shera International
Dear SynaptiCAD,
As a customer of Synapticad products for the past three
years, I want to give you some feedback on your Verilog
simulator and test bench generation tools.
I have used the Verilogger product on three different ASIC
designs for Hewlett-Packard Company and have been
successful in meeting a demanding schedule with fully
functional parts. I contribute my high level of performance
and success to the use of your Verilogger product. The
integrated editor, simulator, interactive debugger and
waveform viewer has provided me with tools to efficiently
design and test various hardware blocks in an ASIC. I have
been able to perform initial verification of various Verilog
hardware blocks using the waveform drawing capabilities of
your product where the test bench is produced automatically
from the waveforms. This has saved me considerable time
during the development process since I can perform an initial
verification without writing a single line of Verilog test bench
code. I can also use the various waveform files for
documentation of the ASIC design.
After I have performed the initial verification, I spend a
considerable amount of time in manually generating a
comprehensive Verilog test bench for the ASIC design with
associated Verilog models. I have recently purchased the
Testbencher product which adds test bench generation
capability to the integrated environment described above. I
have been able to generate Verilog code models for various
peripherals connected to an ASIC under test in record time
without writing much Verilog code. I plan on using
Testbencher for generating comprehensive test benches that
I had previously generated manually and were prone to
many errors. I can generate the various waveform files for
the various models connected to the chip-under test with
self-checking capability (samples) using the integrated
waveform drawing tool and Testbencher generates the
Verilog test bench.
Testbencher is the most complete and comprehensive
Verilog design tool that I have ever used.
Synapticad has an excellent customer service department. I
have communicated various issues with the Synapticad
toolset and have received a response at all times within 24
hours. I appreciate the support and flexibility that Synapticad
has provided to me during my short development schedules.
George Lysy
Hewlett-Packard Company
"I'm impressed with SynaptiCAD, they have a great simulator
at a very accessible price. I found it to be 100% Cadence
Verilog-XL compatible. My test case simulated the same RTL
code from a big FPGA (Xilinx Virtes-300/600/1000 and an
Altera 10k150) in Verilog XL and in VeriLogger with no
problems. Even on a machine with only 128M of RAM,
VeriLogger performed well. The SynaptiCAD staff was very
quick to answer any question and I have always found them
to be very responsive and helpful."
Gill Romero
Principal Consultant, ASIC Alliance Corp.
"Hi Gary,
Just a quick note to let you know how helpful I have found
SynaptiCAD's Verilogger. I am currently working on a design
which involves two clocks, asynchronous with respect to
each other. The timing diagram editor included with
Verilogger helped me design the synchronizing circuit
quickly. I started with a new diagram, added the two clocks
and the synchronizing signal. Then I started adding /
modifying signals until I reached a design that looked good.
Having the ability to draw new signals and specify their
behavior with equations then to see Verilogger's timing
diagram editor correctly simulate the signals really makes the
detail design work go quickly. It means I no longer have to
waste a lot of time sketching stuff out on the whiteboard,
opening an editor, writing the code, creating a test bench
and pulling it into the simulator to verify correct operation.
Verilogger has all this functionality built in. The point-andclick style for creating signals is extremely easy to learn and
use. And it is easy to assign an equation to a signal -- right
click to open the properties for the signal and the equation
box is right there.
Also thanks for pointing out how easy it to specify and
name a group of signals I want to watch as a View into a
particular timing diagram. I have a few groups specified (the
afore-mentioned clocks) and it only takes two clicks to switch
back and forth among them. That really makes it easy to
check out parts of the design and make sure none of my new
"fixes" have broken any of the other code. Thanks again"
Sam Mitchum
Philips Semiconductors
"Hi Gary,
By the way, I really love VeriLogger! I'm using the
command line version in a makefile to automate all my sim
runs for the current project, and then use the GUI for debug.
This will be the first ASIC I've done entirely with VeriLogger
and the price is great!"
Mike Kentley
High Desert Design Center
"Hi Gary,
I've been really happy with your phone support. A few
weeks ago I was working from home and had a problem
working in Waveformer. It was the day after I spoke with you
on the phone and I thought I had remembered you
mentioning that you were going to be at work on Saturday,
so I went ahead and called. I don't remember the name of
who answered, but your phones where being forwarded to
somebody at home. And he got me the help that I needed.
On Saturday. Awesome! "
Jim Means
L3 Communications
"Waveformer Pro has been invaluable to me for working thru
design ideas as well as documenting the design
implementation. One of my recent designs, a Crossbar
Switch Arbiter implemented in an Altera CPLD, was a heavily
pipelined architecture using time division multiplexing.
Waveformer Pro was used to initially brainstorm device
operation and to document how each pipe element worked
and would feed the next element in the pipe. Waveformer
Pro has also been used to document system timing
considerations, which have formed the backbone of a 64Gbit
router design. All timing considerations have been included
in a waveform diagram and timing spreadsheet indicating
how all router line cards must implement the back-end
design. This diagram will become the basis of our system
design documentation. Waveformer Pro has been easy to
use and exactly the tool that today's design engineer needs
to include as part of one's design methodology."
Andrew M. Norton
Norton Engineering Consultants
"The combination of WaveFormer Pro and HP logic
analyzers lets designers use captured waveforms as
stimulus vectors to drive the simulation of a circuit. This
capability allows fast debugging and should help our
customers bring their products to market sooner.”

Customer Success at IBM!
Patrick J. Byrne, General Manager
Hewlett-Packard Colorado Springs Division
As a group of ASIC design engineers we often deal with
chip, interface and system level timings. Powerful simulation
tools are used to verify if the timing design goals were
achieved. Nevertheless, the planning of the timing must be
done with pencil and paper. Documenting the complex
waveforms with the built in drawing tools of a standard word
processing software is another tedious task. And who will
repeat that lengthy procedure when a design modification
requires a slightly changed timing?
The WaveFormer is a valuable tool that bans paper and
pencil from the desk when planning complex timing
diagrams, and it is not more difficult to use. Entering and
editing signals and timing parameters is quickly learned by
doing. Worth mentioning is the fact how fast you handled a
request regarding a bug in WaveFormer Pro 5.1, ... nobody
is perfect, but it would not matter if everybody would respond
as fast as you did.
H. Thielemann, SIEMENS AG, Germany
Mobile Radio Hardware Development
Just thought I would drop you a note to let you know
Panametrics Engineering loves WaveFormer Pro for
designing Viewlogic Simulation stimulus...
Steve Besser
Panametrics Engineering
I had to make a decision a year ago whether to go with
WaveFormer or Timing Designer [by Chronology
Corporation]. I am glad I picked WaveFormer! You have
done a great job adding new features, keep up the good
work.
One request I would like to make: when entering timing
relationships, it would be very nice to just double click on the
timing constraint, and a dialog box pops up with a link
directly into the timing database, so that I can quickly enter a
library timing parameter. This was handy in Timing Designer,
but it isn't enough to switch back ;-)
Follow up email, received 10 minutes later the same day
Sorry about that, I guess I didn't have time to check over all
the new features in this release. It has a much better way of
entering libraried timing parameters via the pop up dialog
box (just didn't see it)!
Stephen Noftall
Level Control Systems
Subject: Many Kudos...
Well, I recieved WaveFormer this morning around 10:30am
and its around 12:30 now. In 2 hours I feel I've gotten a
pretty good feeling for the program. Excellent tutorial. It
shows how to use the software in a real situation but doesn't
belabor the trival stuff. From the doc notes, it seems like
you've been adding significant functionality with each new
release, yet you've been able to keep the program easy to
learn. Given my several previous experiences trying to get
up to speed on CAD programs in a day or so, you have done
an incredible job. Its easy enough to learn and use that I am
already _designing_ system timing in the program, rather
than just entering and checking my hand-written hen
scratches. WOW!
Also, I didn't realize it when I ordered the sotware, but thanks
for not having a dongle. I hate having to carry those darn
things around with my laptop if I take work home. I'm always
scared that someone will steal it or I'll lose it.
Well, I got to get back to the grindstone. Oh, by the way, the
reason that I'm now designing on the system is that after
entering about a dozen waveforms, etc in a complicated
dram controller, I found subtle timing error that now I have to
fix. I suspect that finding this problem early probably just paid
for the tool.
C. Bolton
Bolton Engineering Inc
Subject: WaveFormer Testimonial
I've been using the Waveformer since 1994 and find it to be
an indispensible tool in both design analysis and synthesis.
I've applied the Waveformer to optimize both performance
and cost in product upgrades. I use it to synthesize new
designs as well. It allows me to define my timing constraints
which help to determine what components I will use. Once
chosen, I can re-simulate and use the timing diagrams as a
reference for simulation waveforms. I can freely investigate
scenarios such as matching memory to processor speeds
without the need for schematics or behavioral models. The
timing diagrams are used and re-used from upgrade to
upgrade and from design to new design. The Waveformer is
an important tool which bridges the gap between the worlds
of analysis and synthesis.
Ralf Chlipalski
Senior Design Engineer, Gandalf Canada Ltd.
WaveFormer's instant feedback environment takes the
headache out of system level timing. No digital designer
should be without it!
Mark Knecht
Virtual Chips (Phoenix Technologies)
Direct Sales Line: 800-804-7073 | Phone: 540-953-3390 | Email: [email protected] | Fax:
540-953-3078
Home | Whats New | Search | Downloads | Pricing | TestBencher
VeriLogger | WaveFormer | DataSheet | TimingDiagrammer | Tech Papers | App Notes
Tutorials | EDA Links | Tektronix | Agilent | About SynaptiCAD | Employment | Distributors
COPYRIGHT 2001, SYNAPTICAD INC., ALL RIGHTS RESERVED.
Timing Diagrammer Pro, WaveFormer Pro, TestBencher Pro, VeriLogger Pro, DataSheet Pro and
SynaptiCAD are trademarks of SynaptiCAD, Inc.
All other marks are trademarks of their respective owners.
vhdl verilog SPICE Pspice timing analysis test bench generation ABEL Minc viewlogic vhdl verilog
vhdl verilog vhdl verilog vhdl verilog