Instruction
register
PC
Address
Data
A
Register #
Instruction
Memory
or data
Data
Memory
data
register
ALU
Registers
Register #
B
Register #
Overview of the multi–cycle Architecture Datapath
ALUOut
Multi-cycle Architecture:
• each instruction is executed in several clock cycles
• instruction execution time (machine cycle) is variable
• instructions can store intermediate results (in intermediate registers) to be used
in next stages of execution of this instruction
• the final instruction results are stored either in register file, memory or PC
• reduction of dedicated architecture elements in favor of intermediate registers
Hardware Blocks:
•
•
•
•
common memory unit for both program and data
register file
single general-purpose ALU
intermediate registers at output of each hardware block
Intermediate Registers (not accessible directly)
IR
MDR
A,B
ALUOut
—
—
—
—
instruction register — stores instr. code during whole machine cycle
memory data register — stores the data read from the memory
store the data read from the register file
stores the result of ALU operation
PC
0
M
u
x
1
Address
Memory
MemData
Write
data
Instruction
[25-21]
Read
register 1
Instruction
[20-16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Instruction
[15-0]
Instruction
register
Instruction
[15-0]
Memory
data
register
0
M
Instruction u
x
[15-11]
1
A
B
0
M
u
x
1
Sign
extend
32
Zero
ALU ALU
result
ALUOut
0
4
Write
data
16
0
M
u
x
1
1 M
u
2 x
3
Shift
left 2
Additional multiplexers are required to make the hardware (ALU) available to all
instruction operations (R-type operations, PC increment, memory address
calculation)
Multi–cycle Architecture Datapath with Hardware Sharing
IorD
PC
0
M
u
x
1
MemRead
MemWrite
RegDst
RegWrite
Instruction
[25-21]
Address
Memory
MemData
Write
data
IRWrite
Instruction
register
Instruction
[15-0]
Memory
data
register
0
M
u
x
1
Read
register 1
Read
Read
data 1
register 2
Registers
Write
Read
register
data 2
Instruction
[20-16]
Instruction
[15-0]
ALUSrcA
0
M
Instruction u
x
[15-11]
1
A
B
4
Write
data
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
Zero
ALU ALU
result
0
1 M
u
2 x
3
ALU
control
Instruction [5-0]
MemtoReg
Multi–cycle Control Signals
ALUSrcB ALUOp
ALUOut
PCWriteCond
PCSource
PCWrite
ALUOp
Outputs
IorD
ALUSrcB
MemRead
ALUSrcA
Control
MemWrite
RegWrite
MemtoReg
IRWrite
Op
[5-0]
RegDst
0
M
26
Instruction [25-0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25-21]
Read
register 1
Instruction
[20-16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Instruction
[15-0]
Instruction
register
Instruction
[15-0]
Memory
data
register
0
M
Instruction u
x
[15-11]
1
B
4
Write
data
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
Jump
address [31-0]
Zero
ALU ALU
result
0
1 M
u
2 x
3
ALU
control
Instruction [5-0]
Complete Multi–cycle Architecture
x
2
PC [31-28]
0
M
u
x
1
A
28
1 u
ALUOut
Signal
RegDst
RegWrite
ALUSrcA
MemRead
MemWrite
MemToReg
IorD
IRWrite
PCWrite
PCWriteCond
0
reg. loaded from memory
—
PC to ALU
—
—
ALUOut is to be stored
in the register file
PC addressing the memory
—
—
—
1
reg. modified by R-type
allow to modify the register file
A to ALU
allow to read the memory
allow to write the memory
MDR is to be stored
in the register file
ALUOut addressing the memory
allow to write the IR
allow to write the PC
allow conditionally write the PC
1-bit Control Signals
Signal
Value
ALUOp
00
01
10
ALUSrcB
00
01
10
11
PCSource
00
01
10
Operation
add (load-store)
subtract (branch)
depending on function field (R-type)
B (R-type) to ALU
4 to ALU
instruction[15-0] (load-store) to ALU
instruction[15-0]¡¡2 (branch) to ALU
ALU (PC+4) to PC
ALUOut (branch) to PC
PC[31-26]+IR[25-0]¡¡2 (jump) to PC
2-bit Control Signals
2
(Op
=
6
EQ
')
'B
=
8
ALUSrcA =1
ALUSrcB = 00
ALUOp = 10
Jump
completion
9
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
PCWrite
PCSource = 10
p
(O
=
3
')
W
Memory
access
'S
(Op = 'LW')
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Memory
access
5
MemRead
IorD = 1
4
(Op
Branch
completion
W')
Execution
'S
p=
(O
)
ype
-t
=R
(Op = 'J')
') or
'LW
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
(O
Memory address
computation
1
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
Start
Instruction decode/
register fetch
Instruction fetch
p
0
R-type completion
7
MemWrite
IorD = 1
RegDst = 1
RegWrite
MemtoReg = 0
Write-back step
RegDst= 0
RegWrite
MemtoReg=1
state Diagram of Multi–cycle Control Block
State Machine of the Multi–cycle Control Block
ROM-based Hardware Implementation of multi–cycle Control Block