Embedded System Lab.
Neighbor-Cell Assisted Error Correction
for MLC NAND Flash Memories
Yu Cai1, Gulay Yalcin2, Onur Mutlu1, Erich F. Haratsch4,
Osman Unsal2, Adrian Cristal2,3, and Ken Mai1
1Carnegie
Mellon University, 2Barcelona Supercomputing Center,
3Spain National Research Council, 4LSI Corporation
Daeyeon Son
2015.9.22
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Embedded System Lab.
Introduction

NAND flash memory is widely used in diverse applications, ranging
from mobile electronics to enterprise servers.

Unfortunately, as flash cells down to smaller technology nodes, they
become increasingly vulnerable to circuit level noise, reducing the
probability.

In this paper, ‘NAC’ is proposed for correct error on flash cells by
program interference.

‘NAC’ used the overall distribution and conditional distribution on the
each state the logical values made by inserting electron into flash
cells.
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Program Interference

‘Program Interference’ is occurred by word line and bit line on flash
cells in block on SSDs.

Unit of the page the flash cells is distinguished MSB, LSB page
number for avoid the error as program interference.

But, it can’t be perfect solution for modify the error by program
interference.
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‘ECC’ is not equal to ‘God’

‘Error-Correcting Codes(ECC)’ is provided into SSD to protect the
flash cells by occurring errors.

But, ‘ECC’ has limited capacity and it can happens unexpected errors
into flash cells.
Fate of ‘ECC’ will be the ‘Titanic’ through a long time.
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Classification the threshold voltage

SSDs can classify the threshold voltage on victim cell and neighbor
cell using the survey about distribution on all flash cells.

‘Classification’ through reading the flash cells on the block can
distinguish threshold voltage falls on different logical values.

It can find the changing of threshold voltage state as not corrected by
‘ECC’ on each flash cells.
Example of the ‘Classification’
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Neighbor-cell Assisted Error Correction

‘NAC’ is made for modify the threshold voltage on flash cell which
occurred the error by voltage.
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Flash voltage distribution

The probability density function(PDF) can calculate the equation 4.
2𝑛
𝑝 𝑥 =
𝑝(𝑥, 𝑧 = 𝑚)
(4)
𝑚=1

‘Probability’ can distinguish the ‘conditional distribution’ and the
‘overall distribution’.

‘PDF’ shows threshold voltage distribution on each state of the each
logical values like the Figure 2.

𝑝(𝑧 = 𝑚) is approximately 25% for each possible value of ‘m’ which is
logical value of direct-neighbor aggressor cells.
( 𝑝(11) + 𝑝 10 + 𝑝 00 + 𝑝 01 = 1 )
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Flash voltage distribution

Shapes of the density in figure 2 are the ‘Gaussian Distribution’ as the
‘Standard Normal Distribution’.
Falls of the threshold voltage distribution
State of the
floating gate
10
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00
01
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Flash voltage distribution

Authors’ statistical result shows like that:
1.
2.
3.
It can calculate the optimum read reference voltage between two
neighboring logical states.
‘Raw Bit Error Rate’ can be minimized by factors that control the logical
states.
Conditional distribution can modify the error as program interference
higher than overall distribution.
Sister ‘A’
Sister ‘B’
“ Please don’t fight~ ”
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Optimizing the Read Reference Voltage

‘Probability Density Functions(PDF)’ of cells programmed into State 𝑃𝑖
and state 𝑃𝑖+1 are 𝑓(𝑥) and 𝑔(𝑥).

Error rate by put on one another the threshold voltage of other state
can be formulated as equation 5, 6.
+∞
𝐸𝑟𝑟𝑅𝑎𝑡𝑒𝑃𝑖→𝑃𝑖+1 =
𝑓 𝑥 𝑑𝑥
(5)
𝑔 𝑥 𝑑𝑥
(6)
𝑣
𝑣
𝐸𝑟𝑟𝑅𝑎𝑡𝑒𝑃𝑖+1 →𝑃𝑖 =
−∞

And, total error rate is together added the probability of selected
logical values, the equation can be formulated as equation 7.
+∞
𝐸𝑟𝑟𝑅𝑎𝑡𝑒 𝑡𝑜𝑡𝑎𝑙 = 𝑃0 ×
𝑓 𝑥 𝑑𝑥 + 𝑃1 ×
𝑣
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𝑣
𝑔 𝑥 𝑑𝑥
(7)
−∞
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Optimizing the Read Reference Voltage

Total error rate can be the partial differential by variable ‘𝑣’ and can be
formulated as equation 8.
𝑃0 × 𝑓 𝑉𝑜𝑝𝑡 = 𝑃1 × 𝑔(𝑉𝑜𝑝𝑡 )

(8)
Calculation on exactly number the reference voltage for using
correction the error can make up the function as ‘Gaussian
Distribution’, which can be formulated as equation 9.
𝑃0 ×
1
2𝜋𝜎1
𝑣𝑜𝑝𝑡 −𝜇1
−
2𝜎12
𝑒
𝑓 𝑥 =
2
= 𝑃1 ×
1
2𝜋𝜎
1
2𝜋𝜎2
𝑣𝑜𝑝𝑡 −𝜇2
−
2𝜎22
𝑒
2
(9)
𝑥−𝑚 2
−
𝑒 2𝜎2
Function of the standard normal distribution
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Optimizing the Read Reference Voltage

Equation 11 shows very simple average between threshold voltage of
the 𝑃𝑖 and 𝑃𝑖+1 states.
𝑣𝑜𝑝𝑡

(𝜇1 + 𝜇2 )
=
2
(11)
It proved by figure 3(b) which is measured by using authors’ FPGA
platform for test and check the error in flash cells on testing board.
Center is average of data.
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Optimizing the Read Reference Voltage

In the equation 8, it could decide the bit error rate by variable ‘v’ on
the between 𝑃𝑖 and 𝑃𝑖+1 states.

In the equation 11, frame of the minimum bit error rate on distribution
is mean of threshold voltage both 𝑃𝑖 and 𝑃𝑖+1 states.

So, it can find the very exactly voltage to minimize the bit error rate by
using variable ‘v’ on double area which added the threshold voltage
falls.
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Minimizing Raw Error Bit Rate

Equation of mean the reference voltage can be formulated as
equation 12 that added all area of 𝑃𝑖 and 𝑃𝑖+1 states.
+∞
1
1
𝑄 𝑥 = ×
2
2𝜋𝜎

𝑒
−
(𝑥−𝜇1 )2
2𝜎2 𝑑𝑥
(𝜇1+𝜇2)/2
+
(𝜇1+𝜇2)/2
𝑒
−
(𝑥−𝜇2 )2
2𝜎2 𝑑𝑥
(12)
−∞
Finally, the exactly minimum ‘RBER’ can be formulated as equation
13, 14.
𝑄 𝑥 =
1
2𝜋
+∞
(𝜇2−𝜇1)/2𝜎
𝑥2
− 2
𝑒
𝑑𝑥
=
1
2𝜋
+∞
𝑥
𝑥2
− 2
𝑒
𝑑𝑥
(13, 14)

Variable ‘x’ is ‘signal-to-noise ratio’ that calculated by variance on
distribution of threshold voltage in flash cells.

The minimum ‘RBER’ will be decide by ‘SNR’. (Very important)
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SNR  ‘Overall’ vs ‘Conditional’

‘SNR’ is difference the between normal distribution and target(noise)
distribution.

‘Figure 2’, ‘Table 1’ show that should select the conditional(neighborcell) distribution better than overall(all in block) distribution.
𝑆𝑁𝑅 ↑ → (𝐵𝐸𝑅 ↓)
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Minimizing BER using Conditional Distributions

Optimum read reference voltage can divide the ‘Global’ and ‘Local’.

‘Global’ OPT is mean all distribution of the both neighbor aggressor
cells and victim cell.

‘Local’ OPT is mean same logical state of the both neighbor aggressor
cells and victim cell. (Probability of the each state will be got around
¼).
Ref) Y. Cai et al., “Threshold Voltage Distribution in MLC NAND
Flash Memory: Characterization, Analysis, and Modeling”, DATE 2013, pp. 2.
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Minimizing BER using Conditional Distributions

In figure 5, ‘RBER’ for using exactly between aggressor cells and
victim cell should be calculated by ‘Local’ optimum read reference
voltage.
Random value
in each cells.
Stable value in
each cells.
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‘NAR’ and ‘NAC’

‘Neighbor-cell Assisted Reading(NAR)’ is enough to research about
read reference voltage in all distributions.

But, ‘NAR’ have much read latency on reading the information through
program operation to flash cells.

‘Neighbor-cell Assisted Error Correction(NAC)’ presents simple
solution for replace the ‘NAR’ to better on read latency.
Step 1
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Step 2
Embedded System Lab.
‘NAC’ System

‘NAC Buffer’ into buffer of the SSD in figure 6 is used for store the
current page and neighbor pages.

‘NAC Buffer’ can save the size of 5 pages.
‘NAC’ is implemented the micro-architecture into SSD.
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Embedded System Lab.
Prioritized ‘NAC’

In figure 9, the net number of corrected cells of type-N11 can reduce
the total errors by 58%, 44% and 22% for flash memory at 3k, 10k and
30k P/E cycles.

Prioritized ‘NAC’ can reduce as normal ‘NAC’ operation the various
P/E cycles.
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Policy When Neighbor Cells Have Errors

‘Neighbor-Cells’ can also happen the error by program interference.

But, its probability is very small and ‘ECC’ and ‘NAC’ system can
cover the error case by program interference.
Don’t worry~ It’s enough to correct the error.
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Embedded System Lab.
P/E Cycle Lifetime Evaluation

‘NAC fix N11+N01+N10+N00’ can increase lifetime about using
normal value in range of logical values.

The ECC design cost can be reduced by approximately 40% when
NAC is employed.
𝑁
𝑃𝑐𝑤 =
𝑛=𝐸+1
𝑁
𝑅𝐵𝐸𝑅𝑛 × 1 − 𝑅𝐵𝐸𝑅
𝑛
𝑁−𝑛
(22) Equation of the ECC failure rate
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Performance Evaluation

‘NAC’ is that a hit ratio of data is important because it uses the cache
in SSD.

As result, workloads that only have higher levels of spatial locality, of
which there are fewer, can take advantage of the MSB neighbors.
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Performance Evaluation

The read latency on ‘NAC’ can reduced by ‘NAC buffer’ for save
correcting data about error flash cells.

System with prefetching also can reduced the read latency.

‘NAC’ is efficient for reduce error and correcting latency.
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Conclusion

Error related to program interference are very difficult to determine
about variable for correcting into many word line and bit line.

This paper have researched threshold voltage distribution in logical
values and found efficient method to modify the voltage in flash cells.

‘Neighbor-Cell Assisted Error Correction’ method proposed the
equation for optimized the read reference voltage.

‘NAC’ can reduce the read latency to modify the voltages.
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Embedded System Lab.
References
1.
2.
3.
4.
5.
Y. Cai et al., “Error Patterns in MLC NAND Flash Memory: Measurement,
Characterization and Analysis”, DATE 2012.
Y. Cai et al., “Program Interference in MLC NAND Flash Memory: Characterization,
Modeling, and Mitigation”, ICCD 2013.
Y. Cai et al. “Threshold Voltage Distribution in MLC NAND Flash Memory:
Characterization, Analysis, and Modeling”, DATE 2013.
T. Kim et al., “Cell-to-cell Interference Compensation Schemes Using Reduced Symbol
Pattern of Interfering Cells for MLC NAND Flash Memory”, IEEE Transactions on
Magnetics 2013.
Y. Cai et al. "FPGA-Based Solid-State Drive Prototyping Platform", FCCM 2011.
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