Arithmetic II
CPSC 321
E. J. Kim
Today’s Menu
Arithmetic-Logic Units
Logic Design Revisited
Faster Addition
Multiplication (if time permits)
Goals
• We recall some basic logic gates
• Determine the truth tables for the Boolean
functions
• We recall half-adders and full-adders
• Ripple-carry adders
• Discuss faster adders
Logic Gates
•
AND gate
•
OR gate
•
NOT gate
What are the truth tables?
Logic Gates
•
NOR gate
•
NAND gate
•
XOR gate
What are the truth tables?
Half Adder
a
b
a b
c
s
0 0
0
0
0 1
0
1
1 0
0
1
1 1
1
0
s
c
Full Adder
Give a Boolean
formula for s
cin a b
0 0 0
• s=cin xor a xor b
0 0 1
0 1 0
Give a Boolean
formula for cout
0 1 1
• cout =ab+cin(a xor b) 1 0 0
1 0 1
Design now a circuit
1 1 0
using and, or, xor.
1 1 1
cout
0
0
0
1
0
1
1
1
s
0
1
1
0
1
0
0
1
Full Adder
cin
a
b
s
cout
s=cin xor a xor b
cout = ab+cin(a xor b)
Ripple Carry Adder
Critical Path
cin
a
b
s
cout
Suppose that each gate has a unit delay. What is the
critical path (= path with the longest delay)?
Ripple Carry Adders
• Each gates causes a delay
• our example: 3 gates for carry generation
• book has example with 2 gates
• Carry might ripple through all n adders
• O(n) gates causing delay
• intolerable delay if n is large
• Carry lookahead adders
Faster Adders
Why are
cin a b
cout
cout=ab+cin(a xor b)
they called
0 0 0
0
like that?
=ab+acin+bcin
0 0 1
0
=ab+(a+b)cin
0 1 0
0
= g + p cin
0 1 1
1
Generate
1 0 0
0
1 0 1
1
g = ab
1 1 0
1
Propagate
1 1 1
1
p = a+b
s
0
1
1
0
1
0
0
1
Fast Adders
Iterate the idea, generate and propagate
ci+1 = gi + pici
= gi + pi(gi-1 + pi-1 ci-1)
= gi + pigi-1+ pipi-1ci-1
= gi + pigi-1+ pipi-1gi-2 +…+ pipi-1 …p1g0
+pipi-1 …p1p0c0
Two level AND-OR circuit
Carry is known early!
Carry Lookahead Adders
• Based on the previous identity
Fast because critical path is shorter
O(log n) gate delays [assuming 2-input gates]
More complex to implement
Design is less regular
Layout of one bit adder cells depend on i
• Compromise
couple blocks of carry lookahead adders
Building an ALU
Addition
Subtraction
AND
OR
Binvert
Operation
CarryIn

a
0
1
b
0
2
1

What is missing?
CarryOut
Result
Tailoring the ALU to the MIPS
• Need to support the set-on-less-than instruction
(slt)
• remember: slt is an arithmetic instruction
• produces 1 if rs < rt and 0 otherwise
• use subtraction: (a-b) < 0 implies a < b
• Need to support test for equality (beq $t5, $t6, $t7)
• use subtraction: (a-b) = 0 implies a = b
SLT
• Determine a<b
• Calculate b-a
• If MSB equals
• 1, then a<b
• 0, then a>=b
• Changes?
• Operation less than
• Output of
subtraction
• Overflow
Binvert
Operation
CarryIn
a
0
1
b
0
2
1
CarryOut
Result
a.
CarryOut
SLT
Binvert
Operation
CarryIn
4 operations
• subtraction output
available
• Connect
• MSB set output
•

a
0
1
Result
b
w/ LSB less
0
2
1
Less
3
Set
Overflow
detection
b.
Overflow
Binvert
LSB indicates
whether a<b
•
•
0 if false
•
1 if true
CarryIn
a0
b0
CarryIn
ALU0
Less
CarryOut
a1
b1
0
CarryIn
ALU1
Less
CarryOut
a2
b2
0
CarryIn
ALU2
Less
CarryOut
Operation
Result0
Result1
Result2
CarryIn
a31
b31
0
CarryIn
ALU31
Less
Result31
Set
Overflow
Bnegate
Test for equality
Operation
a0
b0
CarryIn
ALU0
Less
CarryOut
Result0
a1
b1
0
CarryIn
ALU1
Less
CarryOut
Result1
a2
b2
0
CarryIn
ALU2
Less
CarryOut
Result2
a31
b31
0
CarryIn
ALU31
Less
• Notice control lines:
000
001
010
110
111
=
=
=
=
=
and
or
add
subtract
slt
•Note: zero is a 1 when the result is zero!
Zero
Result31
Set
Overflow
Summary
•
•
We can build an ALU to support the MIPS instruction set
•
key idea: use multiplexor to select the output we want
•
we can efficiently perform subtraction using two’s complement
•
we can replicate a 1-bit ALU to produce a 32-bit ALU
Important points about hardware
•
all of the gates are always working
•
the speed of a gate is affected by the number of inputs to the gate
•
•
the speed of a circuit is affected by the number of gates in series
(on the “critical path” or the “deepest level of logic”)
We focused on basic principles. We noted that
•
•
clever changes to organization can improve performance
(similar to using better algorithms in software)
faster addition, next time: faster multiplication