Small sample problem 1:
1.
Consider a computer system that supports multitasking and timesharing. The computer system has the
following properties
• The length of the time slice (quantum) for time sharing is 10ms.
• The system includes two DMAs. Each DMA has a setup time of 4ms. DMA transfer times given below
do not include the setup time.
• Timer interrupts have a higher priority than DMA interrupts.
• Interrupts are queued and cannot be lost.
• Context switches take 1ms.
• There is 64MB of memory available for running processes.
• The scheduler takes 2ms to run
• Virtual memory is not used.
• Three jobs arrive in the following order, A then B then C. All jobs are waiting to begin loading at time
0
• When any one of the following conditions occur the scheduler will run to determine which process
should run next. The scheduler takes a negligible amount of time but requires two context switches to
run (on to load the scheduler, one to load the process it chooses as the next to run)
i. No process is running
ii. A process completes
iii. A DMA setup completes
iv. A timer interrupt completes
Each process (A, B, C) takes 12ms to load its 32MB image into memory ready to begin execution. Process
A has will use 47 ms of CPU, then do a DMA transfer that takes 6ms, then complete 11 additional ms of
CPU use before terminating successfully. Process B will use 6ms of CPU, then complete one 10ms DMA
transfer, then end with 2 additional ms of CPU usage. Process C will run for 44ms then terminate
successfully.
Draw a diagram showing the processes and the utilization of the CPU and the DMAs for the first 50ms after
process A begins to load.
• The timer interrupts are shown in purple
• A DMA interrupt is shown in the diagrams as
.
• The scheduler running is shown in the solution in blue
• The DMA requires a 4ms setup each time it is used.
NOTE THAT PROCESS C IS NOT SHOWN IN THE DIAGRAM BECAUSE PROCESS C DOES NOT
LOAD UNTIL AFTER THE ILLUSTRATED TIME PERIOD. IT IS NOT POSSIBLE TO LOAD PROCESS
C WHILE PROCESSES A AND B ARE IN MEMORY BECAUSE THERE IS INSUFFICIENT MEMORY
AVAILABLE TO LOAD MORE THAN 2 PROCESSES AT THE SAME TIME.
A
B
CPU
DMA1
DMA2
2ms
DMA 1 setup
DMA 1 setup
6ms
DMA 2 setup
12ms
12ms
18 ms
18ms
20ms
24ms
24ms
26ms
32ms
32ms
36ms
36ms
DMA setup
42ms
46ms
48ms
55ms
6ms
DMA 2 setup
56ms
439ms
A
B
DMA setup
48ms
B
29ms
Larger sample problem:
3. Consider a computer system with a CPU, one DMA, input and output hardware and 1 timer.
i. The system has 75000 words of memory (1 word = 64 bits). The first 25000 words of memory are
reserved for the OS dispatcher (and any other O/S code that is needed).
ii. A setup time of 10ms is needed to initialize the DMA for a data transfer. The DMA can transfer up to
2Mb of data at a rate of 50,000 Kb per second (1Kb=1024 bits).
iii. Using the I/0 hardware (not the DMA) a single word takes 3ms to read or write. The CPU busy waits
during the read or write (this particular I/O hardware is not capable of interrupts). Before the data
transfer can begin it takes 1ms to set up the I/O hardware (for each 1 word transfer).
iv. Timer interrupts have a lower priority than DMA interrupts.
v. If a process finishes at the same time as a timer interrupt occurs, the process will be interrupted (the
context switch to the scheduler will happen after the interrupt has been processed, when the process
begins to run again).
vi. If the DMA is using interrupts and the DMA is requested but is not available the DMA request will be
placed in a queue to be run when the DMA is available. The DMA will load the next request from the
queue without intervention from the CPU, It will take 5ms to load the next request from the queue
into the DMA.
vii. Each context switch takes 1 ms. Each of the following constitutes one context switch.
1) When an ISR begins the context is switched from the running process to the ISR. The context of
the process being interrupted is saved and the context of the ISR is loaded.
2) When an ISR ends the context is switched from the context of the ISR to the context of the
process that was interrupted by the ISR. The previously saved context is reloaded.
3) When a process ends the context is switched from the context of the completed process to the
context of the OS dispatcher. The context information saved the last time the OS dispatcher ran
replaces the context of the completed process.
4) When the OS dispatcher finishes the context is switched from the OS dispatcher to the context
of the process chosen by the OS dispatcher to run next.
viii. The processing of the ISR takes a negligi,ble amount of time.
ix.
Running the OS dispatcher to determine the next process takes a negligible amount of time.
Assume the OS dispatcher is running when each part of the problem begins (part a, part b, and part c)
x.
xi.
The OS dispatcher loads the image of the process into the system’s memory (not the process).
Also consider 3 processes, A, B, C
Process A has a memory image filling 12000 words. Process A begins by using 23ms of CPU then it outputs
three words of results.
Process B has a memory image filling 7200 words Process B begins by using 40 ms of CPU. Then process B
uses the DMA to transfer of one 4000 word block of data. Finally, process B uses another 12ms of CPU.
Process C has a memory image filling 28000 words, and is CPU bound for the first 31ms of its execution
then outputs one word of results
a. Consider a system in which the O/S does not support multitasking or scheduling. When the system starts
processes A, B, and C are in the queue waiting to be loaded into the computer system (process A is at the
front of the queue followed by process B, and finally by process C). Assume that a process busy waits while
waiting for I/O (The DMA is configured to use busy waiting rather than interrupts, NO interrupts are being
used by the DMA). Also assume that control is given to the OS dispatcher process whenever a process
completes (the context switches from the running processes to the OS dispatcher). How long would it take
to complete process A followed by followed by process B followed by process C. You must include the time
it takes to load the image from disk into memory using the DMA in your calculations. You may assume the
OS dispatcher process that loads the image is already running when you begin counting how long the
processes A B and C will take to run. Determine the time for each process. You must include a detailed
step by step explanation of how you determined your answers. You must identify the origin of each
contribution to the time it takes to complete process A followed by process B followed by process C (for
example: 10ms are used to set up the DMA to transfer the image of process A).
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Process A must be loaded into memory, dispatcher (already running) needs 10ms to initialize the
DMA and then (12000*64/1024)Kb / (50000 Kb / s) = 15ms to load the memory image into memory.
While the image is loaded the OS process doing the loading is busy waiting.
10+15=25
Once the image is loaded the OS process will cause a context switch taking 1 ms to save the context
of the OS dispatcher and to load the context for process
25+1=26
Then process A runs using 23ms of CPU
26+23=49
Process A sets up the I/0 hardware taking 1ms then writes one word taking another 3ms. This pair
of actions is repeated once for each of the 3 words output.
49+12=61 PROCESS A turnaround time is 61ms
Process A terminates and the OS dispatcher process is loaded needing 1 context switch 1 ms. The OS
dispatcher process decides to load process B.
61+1=62
The OS dispatcher needs 10ms to initialize the DMA
62+10=72
The OS dispatcher busy waits for ((7200*64)/1024)Kb / (50000 Kbytes / s) = 9ms while the image of
process B is loaded into the memory
72+9=81
Once the image is loaded the OS process will cause a context switch taking 1 ms to save the context
of OS dispatcher process and to load process B’s context.
81+1=82
Process B then takes 40ms of CPU.
82+40=122
The DMA is set up taking 10ms
122+10=132
The data for Process B is transferred in (4000*64/1024)Kb/50000Kb/s=5ms, CPU busy waits
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132+5=137
Process B continues for 12ms more CPU
137+12=149
THE TURNAROUND TIME FOR PROCESS B is 149ms
Process B terminates and the context of the OS dispatcher process is loaded. This is one context
switch which take 1ms.
149+1 = 150
The OS dispatcher process loads Process C. It needs 10ms to initialize the DMA and then the 28000
words of image is loaded. The image transfer in
(28000*64/1024)kb / (50000 Kbytes / s) = 35 ms
While the image is loaded the OS process doing the loading is busy waiting.
150+10+35=195
Once the image is loaded the OS process will cause a context switch taking 1 ms to save the OS
dispatcher process and to load process C’s context
195+1=196
Process C then runs using 31ms of CPU,
196+31 = 227
Then to output the word of results the output hardware is set up (1ms) and the word of data is
transferred taking 3 ms.
227+4 = 231
Turnaround times A 61ms B 149ms C 231ms
b. Next consider a different system in which the O/S supports multitasking. Jobs are submitted to the system
and wait in line in the order they are submitted for a chance to be admitted to (loaded into) the system.
This system does not support virtual memory. A job can only be admitted to the system if enough memory
is available to hold the job. If there is not enough memory the job will wait until enough memory is
available before being admitted to the system. The OS dispatcher process admits jobs to the system by
i. Determining if there is enough memory for the job to be loaded. If there is enough memory the OS
dispatcher process sends a request to initialize the DMA to load the image of the job into system
memory. The request is either immediately executed by the DMA or goes into a DMA queue and is
executed at some later time. After the request is sent by the OS dispatcher this step is repeated for
the next job in the queue. If there are no more jobs in the queue waiting to be admitted the OS
dispatcher blocks and the first process in the process queue (if there is one) is loaded. (A context
switch from the OS dispatcher to the first process in the process queue occurs)
ii.
When the image of the job has completed loading the DMA generates an LOAD COMPLETE interrupt. If
a process is running when the CPU receives the LOAD COMPLETE interrupt the LOAD COMPLETE ISR
begins by saving the context of the executing process and placing the executing process at the front of
the process queue. The ISR for the LOAD COMPLETE interrupt always ends by loading the context of
the OS dispatcher process and unblocking the OS dispatcher process. The OS dispatcher process
initializes the new process (the one just loaded) and places it at the end of the process queue. Then the
OS dispatcher blocks and the first process in the process queue and begins to execute (The context is
switched from the ISR to the process that was interrupted). The length of time the ISR takes to execute
can be considered to be the length of time taken by the context switch to the ISR plus the context
switch back to the interrupted process.
You may assume the OS dispatcher process that loads the image is already running when you begin.
You may assume that the time take for the OS dispatcher to run is negligible when compared to the time
taken to context switch to and from the OS dispatcher.
You may assume that when a process completes the context is switched to the OS dispatcher. The OS
dispatcher will try to load any waiting processes into the system (if there is room in memory). Next, it will
switch the context to the context of the first process in the queue (if there is one) and let that process
begin execution.
After the process begins executing the multitasking is of the simplest type. When process 1 completes
setting up the DMA or IO hardware a context switch to the OS dispatcher occurs. The OS dispatcher places
the waiting process (process 1) at the front of the process queue then causes a context switch to the next
(after the one just added to the front of the queue) process in the process queue (process 2). The next
process begins (or continues) executing. If there are no other processes waiting in the queue (there is no
process 2) then let the OS dispatcher try to load another job image. When the I/O that interrupted process
1 is complete (when the interrupt is received) then the process 1 continues to execute, and process 2 is
placed at the front of the queue of waiting processes.
Consider jobs A, B, and C, submitted in that order at time 0. How long does it take to complete jobs A, B
and C? You must include the time it takes to load the image from disk into memory using the DMA in your
calculations. To help you answer this question draw a detailed diagram showing what each job is doing as
a function of time (when it is using the CPU, when it is loading into memory, when it is waiting for I/O) for
the first 220 ms after job A begins to load. Time waiting in a DMA queue should be shown on your
diagram. In your diagram also show what the CPU and each DMA is doing as a function of time. What is the
turnaround time (completion time – submission time) for jobs A, B and C? How do these times turnaround
times compare to the turnaround times for the same jobs in part a?
Note, assume that the memory loaded by process B is in addition to the memory needed by the
image of the process there is not enough space to load job C until job A finishes
Diagram below: Turnaround times A=66 ms increased from 61, B=150 ms decreased from 149ms,
C=184ms decreased from 231.