Topics
•
VHDL register-transfer modeling:
– basics using traffic light controller;
– synthesis.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
VHDL
•
Combines a general-purpose programming
language and an HDL.
– Modeled on Ada programming language.
•
VHDL is a rich language:
– modules;
– abstract data types.
•
VHDL is case-insensitive.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Abstract data types
package lights is
---this is a comment
subtype light is bit_vector(0 to
1);
constant red : light : B”00”;
constant green : light : B”01”;
constant yellow : light : B”10”;
end lights;
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
VHDL entities
•
•
An entity defines the interface to the
module.
May plug various descriptions into the
entity interface:
– behavioral;
– RT;
– gate.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
VHDL constants
•
Bit constant:
– ‘0’, ‘1’
•
Bit vector constant:
– B”0101”
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Traffic light entity declaration
entity tlc_fsm is
port( CLOCK: in BIT; -- machine clock
reset : in BIT; -- global reset
cars : in BIT; -- car signal
short, long : in BIT;
highway_light : out light := green;
farm_light : out light := red;
start_timer : out BIT
);
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
VHDL processes
•
A process is a unit of parallel execution.
– All processes in an entity execute in parallel.
•
•
Processes are used to build up behavior.
Our RT model will have at least two
processes:
– combinational process for the logic;
– sequential process for the flip-flops.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
VHDL process example
combin : process(state,hg)
begin
highway_light <= green;
end process combin;
Event assignment
Modern VLSI Design 4e: Chapter 8
Sensitivity list
Copyright  2008 Wayne Wolf
VHDL formulas
a and b
a or b
not a
a <= b
a=b
after 5 ns
Modern VLSI Design 4e: Chapter 8
Boolean AND
Boolean OR
Boolean NOT
Signal assignment
Equality
time
Copyright  2008 Wayne Wolf
VHDL data types
std_logic
Binary signal
std_logic_vector
Binary signal vector
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Operations in the process
if (b or c) = ‘1’
then
y <= ‘1’;
else
y <= ‘0’;
y assigned value
in both cases
Modern VLSI Design 4e: Chapter 8
if (b or c) = ‘1’
then
y <= ‘1’;
else
z <= a or b;
different net assigned
in true, false cases
Copyright  2008 Wayne Wolf
Conditional assignments
if (b or c) = ‘1’
then
y <= ‘1’;
else
z <= a or b;
•
Simulation:
– Condition is tested
based on current signal
states.
– Only one net gets an
event.
•
Synthesis:
– Creates don’t-cares for
y and z.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Some useful constructs
avec: out std_logic_vector(11 downto 0)
vector
constant zerovec: std_logic_vector(0 to
7) := B”00000000”;
constant vector
sum <= a + b;
adder
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Structure of a VHDL model
•
•
•
Library use statements.
Entity declaration.
Architecture declaration.
– Processes, etc. that form the architecture.
– An entity may have multiple instantiations.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
A synthesizable VHDL
archtiecture
•
•
Declarations of types and signals.
Combinational process.
– May be several combinational processes that
communicate via signals.
•
Synchronous process.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
A synthesizable synchronous
process
sync: process(CLOCK)
begin
wait until CLOCK’event and CLOCK
= ‘1’;
ctrl_state <= ctrl_next;
end process sync;
Ensures evaluation onTransfers
clock edge
next state to present state
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Testbench structure
Unit under test
(UUT)
tester
testbench
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
VHDL testbed organization
•
•
Library calls.
Entity declaration.
– Generally has no inputs or outputs.
•
Architecture section.
– UUT is a component.
– Testbench logic is a process.
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf
Testbench tester process
tester: process
begin
reset <= ‘1’;
clock <= ‘0’;
wait for 5 ns;
Clock tick
clock <= ‘1’;
wait for 5 ns;
assert(highway_light = green);
Checks output of UUT
Modern VLSI Design 4e: Chapter 8
Copyright  2008 Wayne Wolf