Chapter 8
Register Transfer Level
Content
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Register Transfer Level (RTL)
RTL in HDL
Algorithmic State Machines (ASM)
Design Example
HDL Description of Design Example
Binary Multiplier
Control Logic
HDL Description of Binary Multiplier
Design with Multiplexers
Register Transfer Level (RTL)
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Large Digital system design – modular approach
•
modular :constructed from digital device, e.g. register, decoder,
multiplexer etc.
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Register Transfer operation
•
The information flow and processing perform on the data stored
in register
RTL is specified by the following three components:
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The set of register in the system
The operation that are performed on the data stored in the
register
The control that supervises the sequence of operation in the
system
Register
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Register is constructed from F.F. and
gates
1 F.F. =>1 bit register
N F.F. =>n bit resister
Register can perform set, cleared, or
complement
Data processing in register
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performed in parallel during one clock
The result may replace previous data or
transferred to another register
For example
• counter
• Shift register
Statements of RTL
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Transfer: R2←R1
Conditional statement:
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if (T1=1) then(R2 ← R1)
if(T1=1)then(R2 ← R1, R1 ← R2)
Other
• R1 ←R1+R2
• R3 ←R3+1
• R4 ←shr R4
• R5 ← 0
RTL in HDL
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Digital system can be described in RTL
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Verilog HDL
• By means of HDL
• RTL description use a combination of
behavior and data flow
The transfer statement of
Verilog HDL (without a clock)
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Continuous statement:
assign
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S = A+B ;
Procedural assignment (without a clock):
always @ ( A or B )
S = A+B ;
The transfer statement of
Verilog HDL (with a clock)
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Blocking: use “=” as transfer operator
•
executed sequentially
always @ (posedge clock)
begin
RA = RA +RB ;
RD = RA ;
end
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non-blocking: use “<=” as transfer operator
•
executed on parallel
always @ (negedge clock)
begin
RA <= RA+RB ;
RD <= RA ;
end
HDL operators
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Arithmetic :+ 、- 、 * 、 / 、 %
Logical:&& 、 || 、!
Logic:& 、 | 、 ~ 、 ^
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Relational:> 、 < 、 == 、 != 、 >= 、 <=
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Shift: >> 、 << 、 { , }
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• Bitwise or reduction
• True or false
Loop statement
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Repeat,Forever,While,For
Must appear inside an initial or always
block
integer count ;
initial
intial
initial
begin
begin
begin
clock = 1’b0 ;
count = 0;
Clock = 1’b0 ;
while (count <64)
forever
repeat (16)
count = count +1 ;
#5 clock =~clock ; # clock = ~clock ;
end
end
end
for(i=0;i<8;i++)
Logic Synthesis
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The automatic process of transforming a
high-level language description such as HDL
into an optimized netlist of gates that perform
the operations specified by the source code
Designers adopt a vendor-specific style
suitable for particular synthesis tools
HDL constructs used in RTL description can
be converted into gate-level description
Example of synthesis from HDL to
gate structure
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Assign
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always
• assign Y = S ? I1:I0 ;
• Is interpreted as a multiplexer of 2-to-1
• may imply a combinational or sequential circuit
• always @ (I1 or I0 or S)
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if (S) Y=I1 ;
else Y=I0 ;
Always @ (posedge clock)
Always @ (negedge clock)
Process of HDL simulation and
synthesis
Algorithmic State Machine
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Logic design can be divided into two part
• The digital circuits that perform the data processing
•
operation
Control circuits that determines the sequence in
which the various actions are performed
Algorithmic State Machine (ASM)
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A special flowchart that has been developed
specifically to define digital hardware algorithms
Resembles a conventional flowchart, but is
interpreted somewhat differently.
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conventional: sequential
ASM:
• sequence of even
• timing relationship between the states of sequential
controller
• even occurs while going from one state to the next
Three basic elements: state box, decision box,
conditional box
State box
FIGURE 8.3 ASM chart state box
Decision box
FIGURE 8.4 ASM chart decision box
Conditional box
FIGURE 8.5 ASM chart conditional box
ASM block
ASM chart and state diagram
Timing consideration
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Major difference between conventional flow
chart and a ASM chart is in interpreting the
time relation among the various operation
ASM considers the entire block as one unit.
Design example
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Two F.F. E and F
A 4-bits binary counter A (A4,A3,A2 and A1)
A start signal S (starting by clearing A and F)
S=1, increment counter
A3 and A4 determine the sequences of
operations
If A3 = 0, E is clear to 0, count continues
If A3 = 1,E is set to 1,then if A4 = 0, the count
continues, but if A4 = 1, F is set to 1 on next clock
pulse and system stops counting
Then if S = 0, the system remains in the initial
state, but if S = 1, the operation cycle repeats.
ASM chart
Table 8-2
Counter
F.F.
A4
A3
A2
A1
E
F
Conditions
State
0
0
0
0
1
0
A3 = 0 , A4 = 0
T1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
1
0
T2
1
1
0
1
1
1
T0
A3 = 1 , A4 = 0
A3 = 0 , A4 = 1
A3 = 1 , A4 = 1
Datapath for Design Example
RTL Description
State table for control
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Two F.F. G1 and G2
present-state present state
input
next state
output
symbol
G1
G0
S
A3
A4
G1
G0
T0
T1
T2
T0
0
0
0
X
X
0
0
1
0
0
T0
0
0
1
X
X
0
1
1
0
0
T1
0
1
X
0
X
0
1
0
1
0
T1
0
1
X
1
0
0
1
0
1
0
T1
0
1
X
1
1
1
1
0
1
0
T2
1
1
X
X
X
0
0
0
0
1
Logic diagram of control
HDL Description
HDL Example 8-2
//RTL description of design example (Fig.8-11)
module Example_RTL (S,CLK,Cir,E,F,A);
//Specify inputs and outputs
//See block diagram Fig. 8-10
input S,CLK,Cir;
output E, F;
output [4:1] A;
//Specify system registers
reg [4:1] A;
//A register
reg E, F;
//E and F flip-flops
reg [1:0] pstate, nstate; //control register
//Encode the states
parameter TO = 2'b00, Tl = 2'b01, T2 = 2'b11;
//State transition for control logic
//See state diagram Fig. 8-11(a)
always @(posedge CLK or negedge Clr)
if (~Clr) pstate = TO; //Initial state
else pstate <= nstate; //Clocked operations
always @ (S or A or pstate)
case (pstate)
TO: if (S) nstate = Tl; else nstate = TO;
Tl: if (A[3] & A[4]) nstate = T2; else nstate = Tl;
T2: nstate = TO;
endcase
//Register transfer operations //See list of operation Fig.8-11(b)
always @ (posedge CLK)
case (pstate)
TO: if (S)
begin
A <= 4'bOOOO;
F <= 1'bO;
end
Tl:
begin
A <= A + 1'b1;
if (A[3]) E <= 1'bl;
else E <= 1'b0;
end
T2: F <= I'bl;
endcase
endmodule
Testing the design description
HDL Example 8-3
//Test bench for design example
module test_design_example;
reg S, CLK, Clr;
wire [4:1] A;
wire E, F;
//Instantiate design example
Example_RTL dsexp (S,CLK.Clr,E,F,A);
Example_RTL dsexp
(S,CLK.Clr,E,F,A);
initial
begin
Cir = 0;
S = 0;
CLK = 0;
#5 Clr = 1; S = 1;
repeat (32)
begin
#5 CLK = ~ CLK;
end
end
initial
$monitor("A = %b E = %b F
= %b time = %0d".
A.E.F,$time);
endmodule