E906 DAQ Scheme
2011/01/12
Components
• CPUs:
– CODA host (HOST): a powerful server running LINUX.
– CODA run-controller (ROC): VME single board computer running
VxWorks.
• Modules:
– Trigger supervisor (TS): VME 9U. This is a high speed custom trigger
interface designed at Jefferson Lab to coordinate triggers in systems
containing a large number of readout controllers. The Trigger
Supervisor supports up to 12 trigger inputs with pre-scaling by up to
224. ONE for each DAQ system.
– Trigger interface (TI): VME 6U. Receive trigger signal sent from TS. One
BUSY output controlled by ROC.
– VME Front-End-Electronic (FEE): VME 6U. Either CR or TDC in our case.
Its BUSY is ON during “Copy In Progress” (CIP), about 300 ns for 64 bits.
– Trigger decision module (TRIG): VME 6U. CAEN v1495.
POWER UP
• TS set to be BUSY by default(?).
• TI set to be BUSY by default. The BUSY signals
from each FEE are grouped together with TI’s
BUSY and then fed to TS.
Start of a Run
• ROC
– Reset FEE.
– Initialize FEE by any user-defined setting. For example,
number of events stored to be claimed as FIFO full.
– Clear FIFO of FEE.
– Trigger-Enable FEE.
– Clear BUSY of FEE.
• TI: BUSY is clear when the BUSY of all FEEs on the same
crate are cleared.
• TS: clear its own BUSY by software (?) and it become
ready to process the trigger input from TRIG whenever
the BUSY of all TIs are cleared.
First Event
• TS:
– Send out a trigger to all TIs when a valid trigger is received and
satisfies the pre-scaled factor.
– Proper delay by cable lengthen should be added between TRIG and TS
to work as “the common stop” signal for the possible longest drift
time 1.5s in NM4.
• TI:
– Distribute the trigger signal to each FEE on the same crate.
– Send out VME interrupt to ROC. (We might want to make change here
if the read of FEE is not done event by event. What is the mechanism of
implementing “buffered mode”?)
• FEE:
– select the data in the FPGA corresponding to the trigger received.
– Put the data into memory.
• ROC: read data from FEE after receiving VME interrupt.
Event by Event
• TS:
– Send out a trigger to all TIs when a valid trigger is received
under NO-BUSY condition and satisfies the pre-scaled factor.
• TI:
– Send out VME interrupt to ROC. (We might want to make
change here if the read of FEE is not done for each event.)
• FEE:
– Select the data in the FPGA corresponding to the trigger
received.
– Put the data into memory (CIP), about 300 ns for 64 bits.
– (If number of event in the memory reaches the pre-assigned
value, claim FIFO FULL and set BUSY ON.)
• ROC: read data from FEE after receiving VME interrupt.
END of a Run
• TS: set it to be BUSY to block the trigger input.
• ROC:
– Read all data in the FIFO of FEE.
– Trigger-disable FEE.
– Set TI to be BUSY.
Actions of ROC
1. Set up FEE by writing proper values to Control Status
Register (CSR).
2. Write “Trigger Enable” to FEE.
3. Write “Clear BUSY” to TI (I/O register).
4. Trigger received, … (FEE’s busy is ON during the data
conversion).
5. After specified number of triggers received, write “Set
BUSY” to TI (I/O register).
6. Write “Trigger Disable” to FEE.
7. Read data from the FIFO of FEE.
8. Write “Clear FIFO” to FEE.
9. Return to step 2.