VHDL
Structural Architecture
ENG241
Week #5
VHDL Design Styles
VHDL Design
Styles
dataflow
Concurrent
statements
behavioral
(algorithmic)
structural
Components and
interconnects
Sequential statements
• Registers
• State machines
• Test benches
Subset most suitable for synthesis
ENG241/Digital Design
2
Decoder: Data Flow
entity dec_2_to_4 is
port (
A0, A1: in std_logic;
D0, D1, D2, D3: out std_logic);
end entity decoder_2_to_4;
Interface
Example: 2-to-4 decoder
D3
A(1)
D2
A(0)
D1
D0
Signal A0_n, A1_n: std_logic;
begin
A0_n <= not A0;
A1_n <= not A1;
D0 <= A0_n and A1_n;
D1 <= A0
and A1_n;
D2 <= A0_n and A1;
D3 <= A0
and A1;
end architecture dataflow1;
Functionality
architecture dataflow1 of dec_2_to_4 is
A0_n
A1_n
3
Structural VHDL Description
of 2-to-4 Line Decoder
ENG241/Digital Design
4
Structural VHDL Description
(Entity Declaration)
-- 2-to-4 Line Decoder; structural VHDL Description
library ieee;
use ieee.std_logic_1164.all
entity decoder_2_4_w_enable is
port (EN, A0, A1 : in std_logic;
D0, D1, D2, D3 : out std_logic);
end decoder_2_to_4_w_enable;
ENG241/Digital Design
5
Structural VHDL Description
(Components)
architecture structural1_1 of decoder_2_to_4_w_enable is
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
component AND2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
ENG241/Digital Design
6
Structural VHDL Description
(Signals)
A0_n
A1_n
N0
N1
N2
N3
ENG241/Digital Design
7
Structural VHDL Description
(Connecting components)
architecture structural1_1 of decoder_2_to_4_w_enable is
-- component NOT1 declaration
-- component NAND2
signal A0_n, A1_n, N0, N1, N2, N3: std_logic;
begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);
g1: NOT1 port map (in1 => A1, out1 => A1_n);
g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0);
g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1);
g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2);
g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3);
g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0);
g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1);
g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2);
g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);
end structural_1;
ENG241/Digital Design
8
Example – 4-bit Equality
Specifications:
o Input: 2 vectors A(3:0) and B(3:0)
o Output: One bit, E, which is 1 if A and B are
bitwise equal, 0 otherwise
ENG241/Digital Design
9
Design


Hierarchical design seems a
good approach
Decompose the problem into
four 1-bit comparison circuits
and an additional circuit that
combines the four comparison
circuit outputs to obtain E.
1.
2.
One module/bit
Final module for E
ENG241/Digital Design
10
Design for MX module
Define the output of the circuit to be `0’ if both
inputs are similar and `1’ if they are different?
Ei  Ai Bi  Ai Bi

Logic function is

Can implement as
ENG241/Digital Design
11
Design for ME module

Final E is 1 only if all intermediate values are 0
So
E  E0  E1  E2  E3

And a design is

ENG241/Digital Design
12
Overall Design
E  E0  E1  E2  E3
ENG241/Digital Design
13
MX Module: Data Flow
entity mx_module is
port (
Ai, Bi: in std_logic;
Ei
: out std_logic);
end entity mx_module;
Interface
Bi_n
ND_1
Ai_n
ND_2
Signal Ai_n, Bi_n, ND_1, ND_2: std_logic;
begin
Ai_n <= not Ai;
Bi_n <= not Bi;
ND_1 <= Ai and B_n;
ND_2 <= Bi and A_n;
Ei
<= ND_1 or ND_2;
end architecture dataflow;
Functionality
architecture dataflow of mx_module is
Ei  Ai Bi  Ai Bi
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entity ME_module is
port (
A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
E: out std_logic);
end entity mx_module;
Interface
ME Module: Structural
component mx_module
port ( Ai, Bi: in std_logic;
Ei
: out std_logic);
end component;
Signal E0,E1,E2,E3: std_logic;
begin
mx0:
mx1:
mx2:
mx3:
E <=
mx_module
mx_module
mx_module
mx_module
E0 nor E1
port map (A(0),
port map (A(1),
port map (A(2),
port map (A(3),
nor E2 nor E3;
B(0),
B(1),
B(2),
B(3),
E0);
E1);
E2);
E3);
Functionality
architecture structural of ME_module is
E  E0  E1  E2  E3
end architecture structural;
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