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Figure 7.1. Single-bus organization of the datapath inside a processor.
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Figure 7.2. Input and output gating for the registers in Figure 7.1.
Figure 7.3. Input and output gating for one register bit.
MDR inE
MDRin
Figure 7.4. Connection and control signals for
gister
re MDR.
Figure 7.4. Connection and control signals for register MDR.
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Figure 7.5. Timing of a memory READ operation.
Step Action
1
PCout , MAR in , Read, Select4,Add, Z in
2
Zout , PCin , Yin , WMF C
3
MDR out , IR in
4
Offset-field-of-IRout, Add, Z in
5
Z out , PCin , End
Figure 7.7. Control sequence for an unconditional branch instruction.
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Figure 7.8. Three-bus organization of the datapath.
Step Action
1
PCout, R=B, MAR in , Read, IncPC
2
WMFC
3
MDR outB , R=B, IR in
4
R4outA , R5outB , SelectA, Add, R6in , End
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.
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Figure 7.10. Control unit organization.
Control signals
Figure 7.11. Separation of the decoding and encoding functions.
Branch
T4
Add
T6
T1
Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
Figure 7.13. Generation of the End control signal.
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Figure 7.14. Block diagram of a complete processor.
Micro instruction
PCin
PCout
MAR in
Read
MDRout
IRin
Yin
Select
Add
Zin
Z out
R1out
R1in
R3out
WMFC
End
1
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
2
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
3
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
4
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
5
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
6
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
7
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
Figure 7.15 An example of microinstructions for Figure 7.6.
store
Figure 7.16. Basic organization of a microprogrammed control unit.
AddressMicroinstruction
0
PCout , MAR in , Read, Select4,Add, Z in
1
Zout , PCin , Y in , WMFC
2
MDRout , IR in
3
Branch to starting addressof appropriatemicroroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25
If N=0, then branch to microinstruction0
26
Offset-field-of-IRout , SelectY, Add, Z in
27
Zout , PCin , End
Figure 7.17. Microroutine for the instruction Branch<0.
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Figure 7.18. Organization of the control unit to allow
conditional branching in the microprogram.
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Figure 7.19. An example of a partial format for field-encoded microinstructions.
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Figure 7.20. Flowchart of a microprogrm for the Add src,Rdst instruction.
Mode
Contents of IR
OP code
0 1
11 10
0
Rsrc
87
Address
(octal)
Microinstruction
000
4, Add, Zin
PCout, MARin, Read, Select
001
Zout, PCin, Yin, WMFC
002
MDRout, IRin
003
Branch { PC
PC5,4 
Rdst
4 3
0
101 (from Instruction decoder);
[IR10,9]; PC3  [IR 10]  [IR9]  [IR8]}
121
Rsrcout , MARin , Read, Select4, Add,inZ
122
Zout, Rsrcin
123
Branch {PC 170;PC0  [IR8]}, WMFC
170
MDRout, MARin, Read, WMFC
171
MDRout, Yin
172
Rdstout , SelectY
, Add, Zin
173
Zout, Rdstin, End
Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.
Note:Microinstruction at location 170 is not executed for this addressing mode.
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Figure 7.22. Microinstruction-sequencing organization.
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Figure 7.23. Format for microinstructions in the example of Section 7.5.3.
Octal
address
F0
F1
F2
F3
F4
F5 F6 F7 F8 F9 F10
000
001
002
003
0 0 0 0 0 0 0 1 0 0 1 01 1 0 0 1 0 0 0 0 01
0 0 0 0 0 0 1 0 0 1 1 00 1 1 0 0 0 0 0 0 00
0 0 0 0 0 0 1 1 0 1 0 01 0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
121
122
0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01
0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00
1
0
0
1
0
0
0
0
0
1
170
171
172
173
0 1 1 1 1 0 0 1 0 1 0 00 0 0 0 1 0 0 0 0 01
0 1 1 1 1 0 1 0 0 1 0 00 0 1 0 0 0 0 0 0 00
0 1 1 1 1 0 1 1 1 0 1 01 1 0 0 0 0 0 0 0 00
0 0 0 0 0 0 0 0 0 1 1 10 1 0 0 0 0 0 0 0 00
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7.24. Implementation of the microroutine of Figure 7.21 using a
next-microinstruction address field.
(See Figure 7.23 for encoded signals.)
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Figure 7.25. Some details of the control-signal-generating circuitry.
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Figure 7.26. Control circuitry for the bit-ORing.
(Part of the decoding circuit in Figure 7.25.)
LSR
SL
ROR
Control logic
r15
r1 r0
LD
Control lines
and serial input
Figure P7.1. Organization of shift-re
gister control for Problem 7.22.
Figure P7.1. Organization of shift-register control for Problem 7.22.
Clock
A
B
X
Y
Z
Figure P7.2. Digital controller in Problem 7.23.
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Figure P7.3. A microinstruction-sequence pattern used in Problem 7.30.