Design of the 64-channel ASIC: update
DEI - Politecnico di Bari and INFN - Sezione di Bari
Outline
 Proposed solution for the 10-bit ADC
 Status of the design
 Planning and schedule
Meeting INSIDE, December 18, 2014, Roma
A/D conversion: open issue (from the previous meeting)

Dithering, oversampling (with a factor 16) and decimation proposed to increase the resolution of the
available 8-bit ADC to 10 bits
- If the conversion rate of the 8-bit ADC is 20MHz (rather optimistic) we need about Tconv=1ms
for the conversion of one channel
- If we have only one channel to be converted per event and the event rate is 16kHz, roughly, the
probability of losing an event is 2%
- If the event rate is increased of an order of magnitude, this probability becomes about 15%

This solution becomes unacceptable in case we have an appreciable probability that more than one
channel of the ASIC is over threshold for each event. For instance, the conversion of 64 channels
would take 64ms, thus, in this case, we would have a conversion rate of about 15kHz/ASIC (which
would worsen if the 8-bit ADC max conversion rate is less than 20MHz)

According to the discussion in Turin, a conversion rate of at least about 30kHz/ASIC (full 64
channels converted) is needed

Multiple ADC operated in parallel in order to generate more samples at the same time can be a
solution, but this entails more power consumption and problems of effective management of the
ADC resources available among the channels (complex routing and switching)

Alternative solutions must be found
Meeting INSIDE, December 18, 2014, Roma
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Proposed solution: pipeline ADC

It is possible to exploit very simple 1-bit ADC stages in a pipeline structure to increase the resolution of our 8-bit ADC

Only two 1-bit ADC
stages in front of the
8-bit ADC are needed
to
increase
the
resolution to 10 bits
Meeting INSIDE, December 18, 2014, Roma
3
Adding redundancy: 1.5-bit ADC
 To avoid problems due to offset of the comparator used in the 1-bit structure, we add redundancy
 Three possible cases:
Vin < -VREF/8

b1=0 b0=0
-VREF/8 < Vin < +VREF/8

b1=0 b0=1
Vin > +VREF/8

b1=1 b0=1
 The residue is now:
VRES = Vin-(b0+b1-1)VREF/4
 VOUT = 2VRES is the output of the 1.5-bit stage
 In other words we have a three-level quantization, so this stage gives more information than a 1-bit ADC, but
less than a 2-bit ADC
 Two stages in front of our 8-bit ADC provide 4 bits, which are reduced to 2 bits by a very simple digital
decoding circuit
Meeting INSIDE, December 18, 2014, Roma
4
Circuit implementation of the 1.5-bit ADC
 Very simple: two comparators, a three input MUX, some switches and the multiplying stage
 Accurate value of the gain is mandatory: to obtain exactly a gain of 2, switched capacitor structures are used
 The redundancy introduced is able to compensate the comparator offsets e0 and e1 as long as their absolute
values are less than VREF/4, making easier the design of the comparators.
Meeting INSIDE, December 18, 2014, Roma
5
Structure of the 10-bit ADC
 Two 1.5-bit ADC stages, followed by a S&H circuit (needed for decoupling purposes) and the 8-bit ADC
 Timing and phase management
Meeting INSIDE, December 18, 2014, Roma
6
Rate of conversion
 The first conversion takes:
Tconv= TCK (1st 1.5-bit ADC) + TCK/2 (2nd 1.5-bit ADC) + TCK/2 (S&H phase) + 2TCK (AutoZero, Coarse Conversion,
Fine Conversion, Correction phases of the 8-bit ADC) = 4TCK
 If the max clock frequency is 5MHz (rather conservative), TCK=200ns, thus the first conversion takes 800ns
 Thanks to the pipelined structure, the conversion of the other channels take only 1 clock cycle per channel
 In case we must read-out and convert all the 64 channels, this would take 800ns+63*200ns=13.4ms, which
corresponds roughly to 75kHz/ASIC, reasonably more than required.
Meeting INSIDE, December 18, 2014, Roma
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Status of the design
 ADC design finished at layout level: post-layout final verifications to be completed
Block
Circuit
level
Layout
level
Analog channel
x
x
‘Fast’ and ‘slow’ comparators
x
x
Peak detector
x
x
DACs and bias circuits
x
x
ADC interface amplifier
x
x
LVDS buffers and receivers
x
x
Digital part*
x
x
Meeting INSIDE, December 18, 2014, Roma
 All the analog blocks have been defined
at layout level (ADC interface amplifier
included)
 The final layout of the digital part has not
been generated yet
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Planning and schedule

To be done:
-
Flooplan, placement and routing of the blocks
-
According to the floorplan, generation of the final layout of the digital part
-
Assembly of the ASIC
-
Realistic estimation: at least 2 months of work needed

Manpower problems

Next available MPW run deadline: February 2nd, unlikely to be met

Submission expected for the next MPW deadline (April 7th)
Meeting INSIDE, December 18, 2014, Roma
9