Comparison of Thermal dissipation
between diferent package models
Prof. Dr. Marco Antonio Robert Alves
Juliano Fujioka Mologni
Filipe Dias Baumgratz
Edson Fonseca
Presentation topics
• Departament presentation;
• Problem description;
• Metodology;
• Results;
• Conclusions.
DEMIC
Departament of Electronics and Micro-electronics (DEMIC) is part of School of
Electrical and Computer Engineering (FEEC) of UNICAMP.
The research activities at DEMIC are concentrating in the follow areas:
•
Integrated Circuits Projects (Bipolar and MOS);
•
Micro-electronics Technology;
•
Electronics Intrumentation and Measuring;
•
Semiconductors Devices Caracterization and Modeling.
DEMIC works together Research Centers and Government Agencies active in
research promotion and more recently with companies related to their area.
Problem
 Power dissipation per area increase.
•
The operation current and system
dimensions have a direct influence at
power dissipation per area.
•
Since new devices adds more
functions, they will need a higher
current to work.
•
Devices minimum dimensions are
decreasing year by year.
•
Devices temperature rises due to
these factors.
Rising of power dissipation with technology scaling. [1]
•
Threshold voltage and carriers mobility are reduced by temperatura increase.
Mobility of carriers in Si as a function of temperature. [2]
VT 0  MS  2F 
QB QOX QII


COX COX COX
Threshold voltage in a MOSFET with zero bias between
body and source. [6]

MS  Work function difference between metal and semiconduc tor.
2F  Voltage across the semiconduc tor necessary to create a
conduction channel.
QB  Charge in the semiconduc tor under inversion.
QOX  Charge in oxide.
QII  Charge of ion - implantaded impurities in the semiconduc tor.
COX  Oxide capacitance.
VT  VT 0   VSB  2F  2F

Threshold voltage in a MOSFET with nonzero bias between
body and source. [6]
kT  ni 

F 
ln 
q  Na 
Equilibrium electrostatic
potencial in a p-type doped
semiconductor. [5]
N
MS 
kT  ni  Eg
 
ln 
q  N a  2q
Work function difference between metal and
semiconductor in a n-channel MOSFET. [6]
•
Devices performace is worse due to threshold voltage and mobility
decrease..
I DS
k
VGS  VT

2
k
 nCoxW
L
Currente between source and drain. [5]
Threshold voltage influence in saturation current. [4]

2
Metodology
•
2D Model;
•
Simplifications and Considerantions;
•
Adjustaments in inicial model to fit each package
style;
•
Analysing the heating in all packages styles.
Results
 Simulated packages
Package styles. [3]
Standart SOIC
Enhanced Leadframe
Exposed Pad
Conclusions
•
The greater efficiency of Exposed Pad package had been shown by the
simulations.
•
It is not a unespected result once the Exposed Pad package has more “ways” to
lead the heat outside.
•
After shown that Exposed Pad has the beast heat dissipation, we will use his
model to measure the temperature in all points of the package and use this data
as input in more complex simulations. When we can analyze the chip behavior
and how the suround area is affected by chip heating.
References
[1] Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS
Process Technologies, http://hpc.ac.upc.edu/Talks/dir07/T000065/slides.pdf, 1999.
[2] S. M. Sze and Kwong K. Ng, Physics of Semiconductor Devices, John Wiley & Sons,
Inc., Hoboken, New Jersey, 2007.
[3] Freescale Semiconductor, Thermal analysis of semiconductor systems,
http://www.freescale.com, 2008.
[4] Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware, Detection of
Temperature Sensitive Defects Using ZTC, Proceedings of the 22nd IEEE VLSI Test
Symposium, 2004
[5] David A. Hodges, Horace G. Jackson, Resve A. Saleh, Analysis and Design of Digital
Integrated Circuits, McGraw-Hill Education, Singapure, 2003.
[6] J.E. Ayers, Digital integrated circuits : analysis and design, Taylor & Francis e-Library,
2005.