Towards a L1 Pixel track trigger for CMS:
preliminary thoughts & foreseen strategy
Aurore Savoy-Navarro, Paris-Diderot/CNRS &INFN-Pisa
Introductory remarks
• Since now 3 years some of us (starting with S. Kwan & ASN at
LPC/FNAL and discussions in particular with I Shipsey, J. Butler,
W. Smith) are revisiting the possibility /interest to introduce a L1
track trigger based on the pixel information.
• This was first foreseen and studied in CMS by the PSI team and
especially R. Horisberger and collaborators; it was followed by
several simulation studies performed until 2009.
• The idea is indeed not new because this was well developed at
the Tevatron at FNAL by both CDF (L2-SVT in conjunction with
L1-XFT) and more challenging even in BTeV.
• In these brief preliminary presentation we intend to present our
views on how to develop such a L1 pixel TT focusing here on the
hardware part and the impacts on the design of the new ROC
for phase 2.
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Hypotheses of work
• Develop this triggering system in a continuous upgrade and
non-disruptive way from now on until Phase 2
• Following the evolution and continuous upgrade of the Pixel
detector from now, through Phase 1 and up to Phase 2;
• Indeed the pixel detector will be ugraded following the same
basic design (more layers & new pixel sensors) plus new
FEE/readout electronics, in 2 main steps (see next slide)
• while the outer Si tracker will stay as it is till Phase 2, where it
will be replaced by a new detector based on a new design
fitting with its new L1 key-role.
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An important question that motivates
all this past and ongoing activities is
• Can CMS survive until Phase 2, without a L1 track trigger i.e.
until the new outer tracker is installed (around 2024)?
• Some people believe this is possible thanks to improving the
performances of HLT
• Some others believe it is worth to see what could be done
before Phase 2, using the pixel tracker.
• Another fraction of people are exploring in any case the
benefits to also include in the L1 TT for Phase 2, the Phase2
Pixel detector.
This talk reflects the opinion underlined here above in red.
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TIMETABLE: Proposed strategyTowards
following
the LHC and CMS detector upgrades
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Key elements in this R&D activity
1) Study of the Pixel detector characteristics
– asset of the pixel device: its continuous upgrade allows
experiencing in a quite realistic way the evolution of these
performances comparing all-along real data and MC simulations
2) Feasibility studies with the development of a L1-like TT
algorithm (not full reconstruction or HLT-like)
3) To be installed on a Lab benchmarking platform for
optimization and better estimate of trigger performances
(efficiency, rejection power and latency)
4) Preparation of a sectorial demonstrator that will address all
the integration issues especially from the point of view of the
FEE and readout electronics and could at a certain stage be
installed and run in-situ without disturbing the data taking.
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Present status on Point 1) & 2)
• Ongoing studies reported at TTI, DPG-Pixel (Danek Kotinski)
meetings have been achieved with the present Pixel device
and 2011-12 data/MC simu comparison
• Are pursued with simulation studies and Phase 1 and will use
the data taken in the first coming run period to understand
the impact on pixel performances of the new LHC conditions
• MAIN outcomes: our studies are based on
- a gradually increasing Luminosity to reflect the real case
(35,70, 140)
- Our algorithms are based on Pixel CLUSTER and not Pixel
HIT
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Present status on Point 1) & 2) con’td
• We explore 2 approaches for the L1 Pixel TT algorithms:
- Push or standalone
(Chang-Seong’s simu talk yesterday)
- Pull: the Pixel track
trigger segment is driven by
the calorimeters
(e or tau trigger)
&/or the outer tracker
(especially for b-triggering)
(see several presentations on
PiXTRK trigger at TTI, TPSWG)
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Pt 3) Going to Lab benchmarking platforms
Event display developed on
the Lab benchmarking
platform at FNAL when
implementing the PiXtrK
algorithm here tested
with Zee events
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Getting to Pt 4: Benchmarking platforms
These platforms serve as demo-&-learning frameworks with
various Processing Units (PU) in order to:
 Develop a realistic real-time L1 algorithm
(data formatting/handling, pattern recognition & track fitting)
 Compare PU’s scenarios
(FPGA, GPGPU, INTEL Xeon Phi, AM)
 Get realistic estimate of the needed latency & integration
issues in the overall trigger system,
 Implementing the L1 algorithms we are developing.
Collaborative efforts started with Industry/Engineers on:
1) MPC new PU’s technologies for developing ultrafast real
time & highly performing algorithms
2) Modelling/optimizing the architecture of large systems
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Lab Demonstrator - Benchmark Platform
Simulation will run on a heterogeneous platform:
Host system + coprocessors: GPGPU’s / Xeon Phi’s/FPGA’s
– Option 1: all FPGA processing
– Option 2: FPGA+soft GPGPU cores (GPGPU implemented on FPGA)
– Option 3: FPGA + GPGPU and/or Xeon Phi (Nvidia / Intel cards)
Courtesy R. Iope)
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Lab Demonstrator - Benchmark Platform
• Option 1: parallel processes that analyze ROC data fully
implemented on FPGA logic (not sure if it will work)
• Option 2: feasibility studies based on FlexGrip (FLEXible GRaphIcs
Processor for general-purpose computing)
– a fully CUDA binary-compatible integer GPGPU optimized for FPGA implementation
• Option 3: full support from Intel Xeon Phi experts (Intel Software &
Services Group) under negotiation
• Technical support from Intel engineers for the implementation of
the benchmark platform’s host system also under negotiation
– new technologies: 100G network cards, photonics interconnection, storage based on
SATA-Express & ultra-fast SSDs, etc
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Data formatting
Translate bits data from FEE
(ROC) into geometrical data
for P.R. & track reconstruction
at FED output.
Use current pixel device as
“training camp”
Implies full understanding of the FEE readout chain: WORK DONE FOR current FED 2 DATA
(next slide)
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Lab Demonstrator for one vertical sector
Based on the use ATCA platform
Compare performances for L1 algorithm a-la-PiXTRK (as an example)
with all FPGA/VHDL, FPGA+GPU, FPGA+Xeon Phi.
Use current FED2 data as formatted (previous slide) in LUT format in
FPGA to start with.
Option 2&3: FPGA+GPU or
Option 1: All FPGA Processing
FPGA
FPGA
INTEL Xeon Phi
New
Data
PU
formatting
Data
formatting
FPGA
New
PU
FED input data
New
PU
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FED input data
New
PU
FPGA
P.R. + L1
PiXTRK
FPGA
P.R. + L1
PiXTRK
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Outcomes on the design of the FEE
Chip for Phase 2
• This complete framework apart from possibly providing an earlier
pre-HLT or L1.5 track trigger based on the pixel tracker will provide
in addition:
• Instrumental inputs for the design of the new Phase 2 ROC chip
(digitization, sparsification & clustering), its associated readout
system (FED and associated advanced Processing units) and its
integration in the overall DAQ and trigger system of CMS for
Phase 2.
• Apart from showing the interest of including this tracking device in
the overall L1 TT scheme.
• All based on a real life experience with current device and its
upgrade evolution
Our aim is to set-up a task force in this direction and already several
teams are interested or have joined.
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