Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
SOLUTION SET 1
The questions in the set are related to the fundamentals of the VHDL. Topics covered include:
Code structure: libraries, entity, architecture; Data types, Operators, Concurrent statements
and concurrent code.
Solution 1
The following questions must be answered according to VHDL code given below.
1. What is the entity name of the unit : latch
2. What is the architecture name of the unit : dataflow
3. What are the names of input ports : s and r
4. What are the names of output ports : q and nq
5. What are the data types of input ports : BIT type
6. What are the data types of output ports : BIT type
7. How are the statements executed in architecture: In this VHDL code, Concurrently.
8. Which signals are internal signal : q0 and nq0
9. Is there any wrong with internal signal declarations: Yes, Internal signals must be
declared before the “BEGIN” statement.
10. Is there any wrong with input output declarations, if there is, correct it :
r input was declared by IN BIT_VECTORS (3 DOWNTO 0); There are two errors
with this declaration. First error is that data type has syntax error which must be like
BIT_VECTOR and second error is that r input must be one bit not 4 bit width.
11. Is there any wrong with the signal assignments, if there is, correct it :
nq => nq0; q => q0; These signal assignments must be corrected with
nq <= nq0; q <= q0;
VHDL code which is given with some errors in problem 1 is corrected. The code is as
follows:
ENTITY latch IS
PORT (s, r: IN BIT;
q, nq: OUT BIT);
END latch;
ARCHITECTURE dataflow OF latch IS
SIGNAL q0 : BIT := '0';
SIGNAL nq0 : BIT := '1';
BEGIN
q0 <= r nor nq0;
nq0 <= s nor q0;
nq <= nq0;
q <= q0;
END dataflow;
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
Solution 2
Some signals which have different data types are defined below. Some operations which use
these signals are also given below. According to these signals, you must decide whether the
operation is legal or illegal.
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); -- 1D signal
a <= b(5);
b(0) <= a;
y(4) <= d;
a <= e;
y <= a;
c <= d(5);
d(0) <= c;
a <= c;
b <= d;
e <= b;
e <= d;
-- legal (same type: BIT)
-- legal (same type: BIT)
-- y(4) signal has type of STD_LOGIC
-- illegal (type mismatch: STD_LOGIC vs. STD_LOGIC_VECTOR)
-- illegal (type mismatch: BIT vs. INTEGER)
-- illegal (type mismatch: STD_LOGIC_VECTOR
-- legal (same type: STD_LOGIC)
-- legal (same type: STD_LOGIC)
-- illegal (type mismatch: BIT vs. STD_LOGIC)
-- illegal (type mismatch: BIT_VECTOR vs. STD_LOGIC_VECTOR)
-- illegal (type mismatch: INTEGER vs. BIT_VECTOR)
-- illegal (type mismatch: INTEGER vs. STD_LOGIC_VECTOR)
Solution 3
Write a VHDL code for the circuit shown below. Write an expression for D output using only
logical operators (AND, OR, NAND, NOT, etc.).
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
ENTITY CombinationalCircuit IS
PORT ( A, B, C: IN STD_LOGIC;
D: OUT STD_LOGIC);
--input ports declarations
--output port declaration
END CombinationalCircuit;
--------------------------------------ARCHITECTURE Behaviour_CombCir OF CombinationalCircuit IS
BEGIN
D <= not (((A and B) or (not C)) and A);
--operation
END Behaviour_CombCir;
Solution 4
There is a VHDL code below for 8 to 1 (1 bit) multiplexer. VHDL code has some mistakes.
Correct the mistakes so that VHDL code for Multiplexer works properly.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------ENTITY mux IS
PORT ( a, b, c, d, e, f, g, h: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
y: OUT STD_LOGIC
);
END mux;
------------------------------------------ARCHITECTURE mux_behavioral OF mux IS
BEGIN
y <= a WHEN sel="000" ELSE
b WHEN sel="001" ELSE
c WHEN sel="010" ELSE
d WHEN sel="011" ELSE
e WHEN sel="100" ELSE
f WHEN sel="101" ELSE
g WHEN sel="110" ELSE
h;
END mux_behavioral;
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
Solution 5
Explain the operation of the hardware unit which is described by VHDL code given below.
Draw the block diagram and make a truth table according to this VHDL code.
ENTITY black_box IS
PORT (a, b, cin: IN BIT;
s1, s2: OUT BIT);
END black_box;
-------------------------------------ARCHITECTURE dataflow OF black_box IS
BEGIN
s1 <= a XOR b XOR cin;
s2 <= (a AND b) OR (a AND cin) OR (b AND cin);
END dataflow;
The VHDL code describes one-bit full adder. a and b represent the input bits to be added, cin
is the carry-in bit which is used to connect the full adder blocks together, s2 is the sum bit,
and s1 is the carry-out bit. As shown in the truth table, s2 must be high whenever the number
of inputs that are high is odd, while s1 must be high when two or more inputs are high.
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
cin s2
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
s1
0
0
0
1
0
1
1
1
Solution 6
Find the truth table for the following Boolean function and write a VHDL code which
explicitly implements the truth table;
Truth Table
F(x,y,z) = x’y + xy’z+ xz’
x
y
z
F
F(x,y,z) = x’yz’ + x’yz + xy’z + xy’z’ + xyz’
Function given is augmented to find its minterm.
Then, the truth table is found.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
0
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------ENTITY Boolean_function IS
PORT(
x : IN STD_LOGIC; -- Input port declarations
y : IN STD_LOGIC;
z : IN STD_LOGIC;
F : OUT STD_LOGIC -- Output declaration
);
END Boolean_function;
-----------------------------------------------------------------------ARCHITECTURE architecture_BF OF Boolean_function IS
SIGNAL s : STD_LOGIC_VECTOR (2 DOWNTO 0); -- internal signal
BEGIN
s <= x & y& z; -- concatenation operation
WITH s SELECT -- According to select signal, related value is assigned to F output.
-xyz
F <= '1' WHEN "010",
-- values of select can be extracted from function given
'1' WHEN "011",
-- Firstly
'1' WHEN "100",
'1' WHEN "101",
'1' WHEN "110",
'0' WHEN OTHERS;
END architecture_BF;
Solution 7
select
0
0
1
1
0
1
0
1
Q
0
In1
In2
Z
The block diagram and truth table of a multiplexer are shown above. According to the
truth table, the output should be equal to one of the inputs if select = ‘‘01’’ (Q = In1) or
select = ‘‘10’’ (Q = In2), but it should be ‘0’ or Z (high impedance) if select = ‘‘00’’ or
select = ‘‘11’’, respectively.
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
1. Implement this 8 bit 2 to 1 mux using When-Else or With-Select-When statements.
2. Write relevant comments according to your solution.
------- Solution 7: with WHEN/ELSE -------LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------Entity of 8-bit 2 to 1 Mux--------------------------------ENTITY mux IS
PORT ( In1, In2: IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Input ports
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- output port
END mux;
----------------Architecture of 8-bit 2 to 1 Mux --------------------------ARCHITECTURE mux_arc OF mux IS
BEGIN
Q <= "00000000" WHEN sel="00" ELSE -- The output is cleared
In1 WHEN sel="01" ELSE -- In1 input is transferred to the output
In2 WHEN sel="10" ELSE -- In2 input is transferred to the output
"ZZZZZZZZ";
-- High impedance output
END mux_arc;
------------------------------------------Solution 8
Write a VHDL code for 4 to 1 (1 bit) multiplexer unit. After writing that, Write a top level
VHDL code for 4 to 1 (8 bit) mux using 4 to 1 multiplexer which you wrote previously.
------1-Bit 4 to 1 Mux, this is used in 8-bit 4 to 1 mux which is written next page------LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------ENTITY mux_onebit IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END mux_onebit;
------------------------------------------ARCHITECTURE mux_arc OF mux_onebit IS
BEGIN
WITH sel SELECT
y <= a WHEN "00",
b WHEN "01",
c WHEN "10",
d WHEN OTHERS;
END mux_arc;
-------------------------------------------
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------ENTITY mux_Fourbit IS
PORT ( X, Y, Z, W: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END mux_Fourbit;
------------------------------------------ARCHITECTURE mux_Fourbit_arc OF mux_Fourbit IS
COMPONENT mux_onebit IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
Mux0 : mux_onebit PORT MAP(X(0),Y(0),Z(0),W(0),S,Q(0));
Mux1 : mux_onebit PORT MAP(X(1),Y(1),Z(1),W(1),S,Q(1));
Mux2: mux_onebit PORT MAP(X(2),Y(2),Z(2),W(2),S,Q(2));
Mux3: mux_onebit PORT MAP(X(3),Y(3),Z(3),W(3),S,Q(3));
Mux4 : mux_onebit PORT MAP(X(4),Y(4),Z(4),W(4),S,Q(4));
Mux5 : mux_onebit PORT MAP(X(5),Y(5),Z(5),W(5),S,Q(5));
Mux6 : mux_onebit PORT MAP(X(6),Y(6),Z(6),W(6),S,Q(6));
Mux7: mux_onebit PORT MAP(X(7),Y(7),Z(7),W(7),S,Q(7));
END mux_Fourbit_arc;
--------------------------------------------Solution 9
Some signals which have different data types are given below. Some operations are also given
below the declarations. Fill in the blank with the operation result.
SIGNAL a : BIT := '1';
SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";
SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";
SIGNAL d : BIT_VECTOR (7 DOWNTO 0);
SIGNAL e : INTEGER RANGE 0 TO 255;
SIGNAL f : INTEGER RANGE -128 TO 127;
x1 <= a & c;
x2 <= c & b;
x3 <= b XOR c;
-> x1 <= "10010";
-> x2 <= "00101100";
-> x3 <= "1110";
-- x1 5-bit
-- x2 8-bit
-- x3 4-bit
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
x4 <= a NOR b(3);
x5 <= b sll 2;
x6 <= b sla 2;
if b = "1001", then
x6 <= b sla 2; -- operation result ?
x7 <= b rol 2;
x8 <= a AND NOT b(0) AND NOT c(1);
d <= (5=>'0', OTHERS=>'1');
March 20, 2010
EEM 334
-> x4 <= '0';
-> x5 <= "0000";
-> x6 <= "0000"; -- Notice that result
-> x6 <= "0111"; --Grasp the difference with “sll”
-> x7 <= "0011";
-> x8 <= '1';
-> d <= "11011111"; -- only fifth bit is '0'
Solution 10
This is 3-state buffer shown above. Write a VHDL code which describes this 3-state buffer.
You have to use WITH/SELECT/WHEN structure in VHDL code. Notice that input and
output have 8 bit length.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------ENTITY Tri_State_Buf IS
PORT ( in3State: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
enable : IN STD_LOGIC;
out3State: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END Tri_State_Buf;
------------------------------------------ARCHITECTURE Tri_State_Buf_arc OF Tri_State_Buf IS
BEGIN
WITH enable SELECT
out3State <= in3State
WHEN '0',
"ZZZZZZZZ" WHEN OTHERS;
END Tri_State_Buf_arc;
---------------------------------------------
Digital Systems II
Anadolu University
Assist. Prof. Atakan Doğan
March 20, 2010
EEM 334
Solution 11
Some signals and some operations are given. In order to make legal operaitons, you must use
type conversion functions in the assignments below.
Remember : Necessary type conversion functions were given in Lecture Week 4. You can
find easily in the “07-ConcurrSignal.ppt” document. Document is now on webiste of Lecture.
You can also use below functions :
These data conversion functions can be found in the std_logic_arith package of
the ieee library.
• conv_integer(p) : Converts a parameter p of type INTEGER, UNSIGNED,
SIGNED, or STD_ULOGIC to an INTEGER value. Notice that STD_LOGIC_
VECTOR is not included.
• conv_unsigned(p, b): Converts a parameter p of type INTEGER, UNSIGNED,
SIGNED, or STD_ULOGIC to an UNSIGNED value with size b bits.
• conv_signed(p, b): Converts a parameter p of type INTEGER, UNSIGNED,
SIGNED, or STD_ULOGIC to a SIGNED value with size b bits.
• conv_std_logic_vector(p, b): Converts a parameter p of type INTEGER, UNSIGNED,
SIGNED, or STD_LOGIC to a STD_LOGIC_VECTOR value with size
b bits.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric.all;
...Signal Declarations
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_ULOGIC;
SIGNAL f: STD_ULOGIC_VECTOR(3 DOWNTO 0);
SIGNAL g: UNSIGNED (3 DOWNTO 0);
SIGNAL h: SIGNED;
-- Operations
d(2) <= b(7) + a; -- In this addition operation, operands are of type BIT. They cannot be added
together. In order to use addition operation you must use integer type. Therefore, the type
conversion from BIT type to integer must be done. However, there is no direct function to do
it.
b <= d; -- b <= to_bitvector(d); To_bitvector function converts data from std_logic_vector to
bit_vector
e <=d(5) + a; -- Same problem with first one occurs here.
y <= g(1) + g(2); -- These two unsigned numbers cannot be added together. y <= g +
f <= g; -- std_logic_vector(g) must be used.