DOC/LP/01/28.02.02
LP – AP7102
LESSON PLAN
LP Rev. No: 00
Sub Code & Name: AP7102 Advanced Digital Logic System Design
Unit : I
UNIT I
Branch : ME-MAE
Date: 04/09/13
Semester: I
Page 01 of 06
SEQUENTIAL CIRCUIT DESIGN
9
Analysis of Clocked Synchronous Sequential Networks (CSSN) - Modeling of CSSN- State
Assignment and Reduction- Design of CSSN- Design of iterative circuits-ASM chart- ASM
Realization, Design of arithmetic Circuits for Fast adder-Array Multiplier.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
1.
Analysis of Clocked Synchronous Sequential NetworksIntroduction.
50m
1
BB
2.
Design of a Sequential parity checker, Analysis of Moore
and Mealy sequential circuit by signal tracing and timing
charts.
50m
1
BB
3.
Method of constructing state table and state graphs for
Moore and Mealy machines.
50m
1
BB
4.
General Models for a clocked Mealy and Moore sequential
circuits.
50m
1
BB
5.
Guidelines for state assignments and reduction of state
table using state assignment.
50m
1
BB
6.
Different types of State Assignment- Shared row, Multiple
row and One hot state assignment.
50m
1
BB
7.
Determination of state equivalence and circuit equivalence
using an implication table.
50m
1
BB
8.
Design of iterative circuits, Design of a n-bit comparator.
50m
1
BB
9.
Algorithmic State Machine (ASM) Charts- Derivation and
realization of ASM Chart.
50m
1
BB
10.
Design of Arithmetic circuits for Fast adder- Carry look
ahead adder.
50m
4
BB
11.
Array Multiplier – Structure of an 4 X 4 Multiplier circuit.
50m
4
BB
DOC/LP/01/28.02.02
LP – AP7102
LESSON PLAN
LP Rev. No: 00
Sub Code & Name: AP7102 Advanced Digital Logic System Design
Unit : II
UNIT II
Branch : ME-MAE
Semester: I
Date: 04/09/13
Page 02 of 06
ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
9
Analysis of Asynchronous Sequential Circuit (ASC) - Flow Table Reduction-Races in ASCState Assignment Problem and the Transition Table- Design of ASC-Static and Dynamic
Hazards- Essential Hazards- Design of Hazard free circuits- Data Synchronizers- Designing
Vending Machine Controller- Mixed Operating Mode Asynchronous Circuits. Practical
issues such as clock skew, synchronous and asynchronous inputs and switch bouncing.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
12.
Analysis of Asynchronous Sequential Circuit - Design of
Fundamental mode sequential circuit - Primitive state
table, state table reduction and state assignment.
50m
4
BB
13.
Design of Pulse mode sequential circuit- Primitive state
table, state table reduction and state assignment.
50m
4
BB
14.
Problems in Asynchronous Sequential Circuits –Cycles,
Critical race and Non- Critical race.
50m
2,5
BB
15.
Hazards- Static, Dynamic and Essential Hazards.
50m
2,5
BB
16.
Design of Hazard free switching circuits- Static Hazard
and Essential Hazard elimination.
50m
2,5
BB
17.
Working principle of Data synchronizer.
50m
7
BB
18.
Design of Vending machine controller- Description/
Specification, FSM design steps, State diagram and state
table.
50m
4
BB
19.
Design of mixed operating mode asynchronous circuit.
50m
4
BB
20.
Practical issues: Clock skew, synchronous and
asynchronous inputs and switch bouncing.
50m
7
BB
CAT – I
90m
-
-
DOC/LP/01/28.02.02
LP – AP7102
LESSON PLAN
LP Rev. No: 00
Sub Code & Name: AP7102 Advanced Digital Logic System Design
Unit : III
UNIT III
Branch : ME-MAE
Semester: I
Date: 04/09/13
Page 03 of 06
FAULT DIAGNOSIS & TESTING
9
Fault diagnosis: Fault Table Method- Path Sensitization Method- Boolean Difference
Method- Kohavi Algorithm -Tolerance Techniques- The Compact Algorithm. Design for
testability: Test Generation- Masking Cycle - DFT schemes. Circuit testing fault model,
specific and random faults, testing of sequential circuits, Built in self test, Built in Logic
Block observer (BILBO), Signature analysis.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
21.
Fault Models- Stuck-at fault, Bridging fault, stuck-open fault
and Temporary faults.
50m
3
BB
22.
Fault Diagnosis of Digital systems- Test generation for
combinational logic circuits- Fault Table Method and Path
Sensitization method.
50m
2
BB
23.
Boolean Difference method.
50m
3
BB
24.
Kohavi and Compact Algorithm.
50m
2
BB
25.
Tolerance techniques- Static redundancy, Dynamic redundancy
and Hybrid redundancy.
50m
3
BB
26.
Self- purging redundancy, Sift-out modular redundancy
50m
3
BB
27.
Fault in PLA’s, Test generation and Masking cycle.
50m
2
BB
28.
Design for Testability (DFT), DFT schemes, Circuit testing
fault model: Specific and random faults.
50m
4
BB
29.
Testing of sequential circuits and Built In Self Test (BIST).
50m
4
BB
30.
Built In Logic Block Observer (BILBO) and Signature
analysis.
50m
4
BB
DOC/LP/01/28.02.02
LP – AP7102
LESSON PLAN
LP Rev. No: 00
Sub Code & Name: AP7102 Advanced Digital Logic System Design
Unit : IV
UNIT IV
Branch : ME-MAE
Date: 04/09/13
Semester: I
Page 04 of 06
PERFORMANCE ESTIMATION
9
Estimating digital system reliability, transmission lines, reflections and terminations, system
integrity, network issues for digital systems, formal verifications of digital system: modelchecking, binary decision diagram, theorem proving, circuit equivalence.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
31.
Estimating Digital System Reliability- Failure rates,
Reliability and MTBF, System Reliability.
50m
9
BB
32.
Transmission lines with infinite and finite length
terminated with characteristic impedance, Logic
signal terminations.
50m
9
BB
33.
Network issues for digital systems: Noise, Time
margin, Parasitic inductance and capacitances.
50m
9
BB
34.
Digital System Integrity to minimize Noise Margin,
Transmission Line effects, Signal Path Return
currents and power distribution.
50m
9
BB
35.
Design and Verification of Digital Systems: Design
flow and RTL Verification.
50m
9
BB
36.
Binary Decision Diagrams with an example.
50m
9
BB
37.
Model for Design Verification, Functional
Validation.
50m
9
BB
38.
Formal Verification and Challenges in Symbolic
Simulation.
50m
9
BB
CAT II
90m
-
-
DOC/LP/01/28.02.02
LP – AP7102
LESSON PLAN
LP Rev. No: 00
Sub Code & Name: AP7102 Advanced Digital Logic System Design
Unit : V
UNIT V
Branch : ME-MAE
Semester: I
Date: 04/09/13
Page 05 of 06
TIMING ANALYSIS
9
ROM timings, Static RAM timing, Synchronous Static RAM and its timing. Dynamic RAM
timing, Complex Programmable Logic devices, Logic Analyzer Basic Architecture, Internal
Structure, Data display, Setup and Control, Clocking and Sampling.
Session
No.
Topics to be covered
Time
Ref
Teaching
Method
39.
Read Only Memory (ROM) – Timing diagram.
50m
7
BB
40.
Static RAM – Internal Structure and Timing
parameters for Read and Write operation of static
RAM.
50m
7
BB
41.
Synchronous SRAM- Internal Structure and its read
and Write operation.
50m
7
BB
42.
Dynamic RAM – Structure, Write and burst read cycle
Timing.
50m
7
BB
43,44
Complex Programmable Logic Devices general
architecture, Function block architecture, Input/output
block architecture and Switch Matrix.
100m
7
BB
45.
Logic Analyzer- Basic Architecture and Internal
Structure.
50m
6
BB
46.
Logic Analyzer- Clocking, Triggering, Acquisition and
Capturing Glitches.
50m
6
BB
50m
6
BB
90m
-
-
47.
Logic Analyzer- Data display, Setup and Control
CAT III
DOC/LP/01/28.02.02
LP – AP7102
LESSON PLAN
LP Rev. No: 00
Sub Code & Name: AP7102 Advanced Digital Logic System Design
Branch : ME-MAE
Semester: I
Date: 04/09/13
Page 06 of 06
Course Delivery Plan:
1
Week
2
3
4
5
6
7
8
9
10
11
12
13
I II I II I II I II I II I II I II I II I II I II I II I II
I
1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 5 5 5
Units
CAT I
CAT II
CAT III
REFERENCES:
1
2
3
4
5
6
7
8
9
Charles H.Roth Jr “Fundamentals of Logic Design” Thomson Learning 2004.
Nripendra N Biswas “Logic Design Theory” Prentice Hall of India,2001.
Parag K.Lala “An Introduction to Logic Circuit Testing” Morgan and Claypool
Publisher, 2009.
Stephen D Brown. “ Fundamentals of digital logic”, TMH Publication,2007
Balabanian,” Digital Logic Design Principles” Wiley Publication, 2007
Stalling, “Computer Organisation & Architecture”, Pearson Education India, 2008.
J.F. Warkerly, “Digital Design”, Pearson Education India, 2012.
J.F. Warkerly, “Digital Design principles and practices”, PHI publications, 2005.
Charles J. Sipil, Microcomputer Handbook McCrindle-Collins Publications 1977.
Prepared by
Approved by
Name
M.Athappan
Dr.S.Ganesh Vaidyanathan
Designation
Assistant Professor/EC
HOD/EC
Date
04-09-2013
04-09-2013
Signature