Chip
Designation
Number of
Devices
Set 0
P2
1
1
100%
1
100%
100%
Set 1
(AFSiD)
W14D3_a
2
1
50%
0
0%
0%
W14D5_a
2
1
50%
0
0%
0%
AS2_0_3
1*
1
100%
0
0%
0%
AS2_1_3
1*
1
100%
0
0%
0%
AS2_0_3
4
3
75%
3
100%
AS1_2_3
2*
2
100%
0
0%
AS2_3_3
2*
1
50%
AS0_-1_3
4
3
75%
2
67%
AS2_-1_3
4
3
75%
3
100%
AS2_1_3
5
4
80%
4
100%
Total
(Set 3.0 + 3.1)
21
16
76%
12
75%
(80%)†
Total
28
21
75%
Yield
Handled Yield
Heated Yield
LA Yield
Final
Yield
Set 2
Set 3.0
Set 3.1
3
100%
(3)
(100%)
0 (mechanical
failure - broken
bonds)
Summary of results for Laser annealing survivability test.
Testing still in progress.
Set 0 is the first LA test, done on implanted device. The
annealed device recovered from implant damage.
‘Handled’ involves taking the chips through LA process
with no equipment turned on.
Set 1 was an attempt to recreate the results of Set 0. The
devices did not survive, suspected a static issue.
‘Heated’ involves everything except the laser.
Set 2 used different devices. We have more, and the
devices themselves have higher yields than AFSiD
devices.
‘LA’ is the full laser anneal process.
* Devices were received already bonded
†
80% yield when ignoring mechanical failure
Set 3.0 and Set 3.1 are being processed in parallel. The
Set 3.0 chip is one step ahead of Set 3.1, allowing us to
find and correct problems without loss of all devices.
1
First laser anneal test (P2). Device was
implanted with 14keV P+ ions, and IDS showed
decreasing channel conductance. The device
recovered partially between implant and retesting prior to laser anneal test, and further
after annealing.
Sample IV curve for subsequent failed test.
Device is WPOMP1D2 from W14D5. Red
curve shows expected MOSFET action
before the test, which is lost (blue) after laser
annealing.
Before (right) and after (left) IV curves for RTA test. (23/07/2010, ANU)
Failure mode suggests migration of dopants from leads into channel.
Chips had wire bonds removed, then remaining Al etched with acid bath
before rebonding.
2