CA 2007
Project 1
– Pipelined CPU using Verilog –
Yeh-Juin Lin (林業峻)
[email protected]
5/14 2007
Project 1
– Pipelined CPU using Verilog –
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Write a Verilog behavior Pipelined Cycle CPU program
Required Instruction Set：
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and
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add
sub
mul
lw
sw
beq
j
addi
Requirement
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Register File：32 Registers
Data Memory：32 Bytes
Data Path & Module Name
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(In page 6)
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MUL OpCode：
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Hazard handling
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Data hazard:
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implement the Forwarding Unit to reduce or avoid the stall cycles.
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The data dependency instruction follow “lw” must stall 1 cycle.
Control hazard:
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Branch result must be find in ID stage.
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The instruction follow ‘beq’ or ‘j’ instruction must stall 1 cycle.
Requirement (Cont’d)
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Source code (put all .v file into “code” directory)
– TestBench (Design by yourself~!)
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Report (project1_teamXX.doc)
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Initialize storage units
Load instruction.txt into instruction memory
Create clock signal
Output cycle count in each cycle
Output Register File & Data Memory in each cycle
Print result to output.txt
Members & Team Work
How do you implement this Pipelined CPU.
How do you implement the TestBench.
Problems and solution of this project.
Put all files and directory into project1_teamXX.rar
Due Date
• Deadline:
– Deadline: 6/4 (3 weeks)
• Before the Project
– Team work, 3 persons at most
– Please reply the title about ” Project分組” in the forum.
– Must include student ID and student name.
Data Path & Module Name