5. Gate Level Combinational Logic Design
Four-bit Series Adder
Circuits that are designed with modules and then cascaded have a ripple effect associated with
them. The 4-bit series adder has seven gates delays td
S0 2t
a0
HA0
d (the time it takes to signal to propagate through a gate).
This means that the sum is not available until seven
COUT0
b0
1 td
gates delay after the added signals occurred simultaneously at the inputs of adder.
CIN1
The circuits of parallel adders are complicated.
S1 3t
FA1
d
a1
b1
COUT1
CIN2
S2
FA2
a2
b2
COUT2
CIN3
5.2.2. Binary Subtractors
3td
5td
5td
S3
FA2
a3
b3
COUT3
7td
Just like the half adder and the full adder, it is also
desirable to specify and design a half subtractor and full
subtractor so that larger subtractors can be built
iteratively. If we designate a0 as a minuend bit, b0 as a
subtrahend bit, DIF0 the difference bit, and BOUT0 as
the borrow-out bit, then the following truth table of
binary half-subtractor is possible.
a0
0
0
1
1
7td
b0
0
1
0
1
DIF0
0
1
1
0
BOUT0
0
1
0
0
The difference is the arithmetic operation: DIF0  a0 – b0. A borrow bit BOUT0 borrow
from bit 1 if necessary. When borrow is performed, then 2 (binary 10) is added to the minuend
bit, bit a0.
Minimum SOP expressions for the outputs DIF0 and BOUT0 of the half subtractor can
be written as follows:
DIF0 = a0 b0 + a0 b0  a0  b0;
BOUT0 = a0 b0 .
Observe that the expression of function DIF0 is the same as function S0 of the half adder.
The logic diagrams of the half-subtractor are shown in picture.
54
a0
b0

a0
b0

1
DIF0

a0
b0
1
DIF0
a0
b0

BOUT0
5. Gate Level Combinational Logic Design
The output DIF for the binary full subtractor (DIF1 for the first bit full subtractor)
DIF1  a1 – b1 – BIN1 (BIN1  BOUT0).
When borrow out is necessary (BOUT1  1), 2 (binary 10) is added to bit a1.
Now the truth table for the full subtractor of the first bit can be filled in as follows.
a1
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
BIN1
0
1
0
1
0
1
0
1
DIF1
0
1
1
0
1
0
0
1
BOUT1
0
1
1
1
0
0
0
1
Expressions for the DIF1 are the same as for the function S1 of the full adder:
DIF1 = a1 b1BIN1 + a1 b1BIN1 + a1 b1BIN1 + a1 b1BIN1 = a1 b1BIN1.
BOUT1 = p1 + p2 + p3 = a1 BIN1 + a1 b1 + b1 BIN1.
a1 b1 BIN1
00
0
p1
a1 b1 BIN1
01
11
1
10
00
1
01
11
10
1
1
1
0
DIF1
p2
BOUT1
1
1
1
1
1
p3
The logic diagrams of the full subtractor and its symbol are shown in the picture.
Example 5.1
Draw a functional diagram of a series 4 bit
subtractor.
Note
The logic diagrams are made up from logic
gates; the functional diagrams are made up
from functional devices, such as half adder,
full adder, half subtractor, full subtractor,
and from gates.
a1

1
BOUT1
BIN1
a1
b1
BIN1
1
1
DIF1
a1

b1
BIN
b1
a
b

FS
DIF
B
DIF
BOUT
BIN1
5.2.3. Other Arithmetic Devices
We will design an arithmetic device which realizes the function Y  2X 2 + 1, where
X  0, 1, 2, 3, 4.
55
5. Gate Level Combinational Logic Design
The first step of combinational logic design is description of the logic function. The logic
function is described in full by the equation written above.
The second step is setting up of logic functions and logic variables. The logic variable X
is three bit binary digit: X  x2x1x0. The maximum value of function Y is 242+1  33. It means
that Y is six bit binary digit: Y  y5y4y3y2y1y0.
The third step is filling in the truth table.
x2
x1
x0
y5
y4
y3
y2
y1
y0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
1
x
x
x
x
x
x
1
1
0
x
x
x
x
x
x
1
1
1
x
x
x
x
x
x
Observe that the values of function, corresponding to X  5, 6, and 7 are don't care
outputs. According the truth table
y0  1, y1  x0, y2  0, y3  x2 x1 x0, y4  x2 x1 x0, y5  x2 x1 x0.
The fourth step is minimizing of logic functions. According Karnaugh maps in the
picture minimized functions y3, y4, and y5 can be written as follows:
x2 x1x0
00
x2 x1x0
x2 x1x0
01
11
10
1
0
00
p1
01
11
10
p1
1
0
1
x
x
x
01
11
1
x
x
10
0
y5
y4
y3
00
1
x
x
1
x
x
p1
+5 V
y3  p1  x1 x0, y4  p1  x1 x0, y5  p1  x2.
The fifth step is drawing of logic diagrams
corresponding to expressions of minimized functions.
x0
x1
y0
y1
y2

y3
x2

y4
y5
5.2.4. Binary Comparators
We will now show the design of a comparator. A binary comparator is a combinational circuit
that can be used to compare the relative magnitudes of two binary numbers. First we will
consider a half comparator that can handle the two least-significant bits of the binary numbers,
then we will consider the full comparator.
56
5. Gate Level Combinational Logic Design
The truth table below represents the logic description of half comparator used to compare
two LSB of binary digits A and B.
a0
0
0
1
1
b0
0
1
0
1
a0 b0 a0 b0 a0 b0
0
1
0
1
0
0
0
0
1
0
1
0
Minimum SOP expressions can be written directly from the truth table:
a0 b0  a0b0, a0 b0  a0b0 + a0b0  a0  b0, a0 b0  a0b0.
Draw logic diagrams for half comparator self dependently.
The truth table below represents the logic description of full comparator used to compare
two binary digits A and B. Full comparator has five inputs: three outputs of the low position bit
and two inputs of compared bits. It means that truth table of the full comparator has 32 rows.
a0 b0
( IN)
a0 b0
( IN)
a0 b0
( IN)
a1
b1



0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
0
1
0
0
0
1
0
0
x
x
x
x
1
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
1
0
0
1
x
x
x
x
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
1
0
0
1
0
x
x
x
x
0
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
57
5. Gate Level Combinational Logic Design
Although the table for the full comparator looks formidable, it is easy to fill in. Only 12
outputs entries must be determined. The remaining output entries result in don't care output
conditions, since they represent input combinations that can not occur. For example, don't care
outputs occur in the table for minterm 01100 which cannot happen, since a0  b0 cannot be true
at the same time a0  b0 is true. Each of the other don't care outputs represents a similar
situation.
Minimum SOP expression for output  is obtained using the Karnaugh maps shown in
picture below:
  p1 + p2 + p3  a1 b1 +  IN  a1 +  IN  b1
IN0 IN IN a1 b1

00
01
11
10
00
x
x
x
x
01
0
1
0
0
11
x
x
x
x
10
0
1
0
0
p1
IN1 IN IN a1 b1
p2
p3
00
01
11
10
00
x
x
x
x
01
0
1
0
0
11
x
x
x
x
10
0
1
0
0
Example 5.2
Write minimum SOP expressions for other outputs of full comparator. Draw a logic diagram of full
comparator.
Example 5.3
a0 = =
AB
a1
Draw a functional diagram of a series 4 bit comparator (symbol of this comparator is
a2
shown in picture).
a3
A=B
5.2.5. Code Converters
b0
b1
b2
b3
AB
The circuit that performs code conversion (from binary to Gray, from Gray to binary, from one
binary code to another binary code and so on) is called a code converter. The "from" code
represents the inputs and the "to" code represents the outputs in a truth table representation.
Karnaugh maps can then be used to obtain minimum SOP expressions, from which logic or
functional diagrams can be generated for the code converter.
58
5. Gate Level Combinational Logic Design
59