CE 454
Computer Architecture
Lecture 6
Ahmed Ezzat
The Digital Logic,
Ch-3.3, 3.4,
1
Outline
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Memory
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CPU and Buses
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2
Latches
Flip-Flops
Registers
Memory Organization
RAMs and ROMs
CPU Chips
Computer Buses
Bus Width
Bus Clocking
Bus Arbitration
Drawing Conventions
Reading Assignment: Ch 3.5, 3.6
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Memory
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So far we saw only memory-less digital functions
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But we need to store the program, the data and the intermediate
values used by an application running on a processor
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We know from ISA that there are registers and memory
– where does data in “ADD R4, R6” reside?
– What are these R4, R6 “registers”?
– how do they work?
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How are they constructed?
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3
will explain using gates
 in a way similar to combinational logic
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Memory
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Are made from sequential circuits
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But require feedback:
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Require timing to be taken into account
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will assume non-zero gate delay
will introduce the concept of “clock”
New state: a boolean function which depends on
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4
new “state” = F(current state, inputs)
inputs from T earlier
state from T earlier
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Memory: Set-Reset (SR) Latches
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5
A Set-Reset (SR) Latch
– Q and Q’ are fed back as inputs
making it sequential
A bi-stable circuit that stores binary
values
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– Q=1, Q=0 is a “1” state
—
– Q=0, Q=1 is a “0” state
Can only be in one of these states
– output change requires S and R
to be applied
– if S=R=0 then Q remains
unchanged
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Memory: Set-Reset (SR) Latches
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6
S
1
R
0
Q
1
Q’
0
0
0
1
0
0
1
0
1
0
0
0
1
1
1
Set State
Reset State
Undefined
S=R=1 leads to an unstable state. The output Q may “oscillate” before
settling down to either 1 or 0.
if S=R=0 then Q remains unchanged
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Memory: Set-Reset (SR) Latches
Summary
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SR inputs and the resulting state
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Q’ = NOT Q
output change requires either S=1 or R=1 to be applied
Once input is removed the latch “remembers”
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7
SR = 11 is not allowed
 electronically unstable state...
Can only be in a state such that
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SR = 10  Q=1, Q’=0 (“1” state)
 when SR goes to 00 state remains the same: Q=1, Q’=0
SR = 01  Q=0, Q’=1 (“0” state)
 when SR goes to 00 state remains the same: Q=0, Q’=1
SR = 00 then Q remains unchanged
stays in the same state
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Memory: Set-Reset (SR) Latches
Time Diagram
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In an SR latch output Q follows input changes
Note the delay (lag) between input changes and output changes
1
S
R
0
1
0
1
2t
Q
Q
8
t
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t
0
1
2t
0
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Memory: Set-Reset (SR) Latches
Problems with SR Latches
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9
Combinational functions take time to settle
– output may vary for a while before going to correct value
If S,R change then Q will change
– with many levels of gates the change propagates for a while
 may not “settle” in time
We assume that T is the delay of a NOR gate
How long we need to wait for R or S to be stable at 1 so as
– Q is stable at 0
– Q is stable at 1, respectively
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Memory: Set-Reset (SR) Latches
Problems with SR Latches
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How to make sure changes to registers occur
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Modify the latch
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when desired; once per cycle !
incorporate a clock signal as one of the inputs
Will design a computer with many latches
How to make sure things happen when required?
Consider a basic arithmetic operation
Take data from 2 registers
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Run through the ALU
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Store to another register
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Need to make sure these three steps occur at the right time
Solution: generate and distribute a special signal called clock
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keeps time: acts as a conductor for an orchestra or a drummer in a band
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To ensure change occur: when desired only once per clock cycle
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10
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Memory: Clocked SR Latches
 Q only changes when the Clock is a 1.
 If Clock is 0, neither S or R reach the NOR gates.
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Memory: Clocked SR Latches
Still We have Problems
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Undefined state (S=R=1)
Latency of Inputs/clock
– Inputs can change as long as clock is (still) high
 One half of the clock cycle
– That’s too long
A solution - The D-latch
Then we can play with duty cycle to limit when high
– percent of clock cycle that is “1”
– generate a very narrow “1” clock pulse
 but it is hard, especially at 2 GigaHertz
– “sample” input (D) only when clock is “1”
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Memory: Clocked D Latches
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Avoid S=R=1; only one input
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If D is a 1 when the clock
becomes 1, the circuit will
remember the value 1 (Q=1).
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If D is a 0 when the clock
becomes 1, the circuit will
remember the value 0 (Q=0).
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Memory: Clocked D Latches
Narrow Clock Pulse (~5 nsec)
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Memory: Flip-Flop (Master/Slave)
1
D
0
1
C
0
1
Q
15
0
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Memory: D Latches vs Flip-Flop
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(a): is a D latch whose state is loaded when clock is 1
(b): is a D latch whose state is loaded when clock is 0
(c): is a F/F change state on the rising edge of the clock pulse
(d): is a F/F change state on the falling edge of the clock pulse

Some latches and F/Fs provide also Q as output, and Set and
Reset as additional inputs
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Memory: Registers
8-Bit Register
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We can use 8 D Latches to
create an 8 bit memory.
We have 8 inputs that we want
to store, all are written at the
same time.
All 8 latches use the same
clock.
D0
D Latch
Q0
D1
D Latch
Q1
D2
D Latch
Q2
D3
D Latch
Q3
D4
D Latch
Q4
D5
D Latch
Q5
D6
D Latch
Q6
D Latch
Q7
D7

clock
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Memory: Registers
Register Notations
A
Data_in[7:0]
Data_out[7:0]
Clock
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Notationally registers are referred to as one unit instead of
addressing each storage element individually.
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Memory: Memory Organization
Random Access Memory (RAM)
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Access time
– from address to data out
Constant access time
– independent of address
– unlike tape or disk
Semiconductor memory:
– RAM
– ROM
Many bits on one IC
Each bit is a “latch”
Depending on type get
– Static
(SRAM)
– Dynamic (DRAM)
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Speed, cost, size relationship:
Speed
Cost
Capacity
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Memory: Memory Organization
Logic diagram for 4 x 3 Memory
 4 rows of clocked D latches,
each is a 3 bits.
 3 input data lines (I0 .. I2)
 2 input address lines (A0, A1)
 3 output lines (Q1 .. Q2)
 CS (clock) line
 RD (READ/Write) line
 OE (output enable) line
 For Read, input lines are not
used. For Write, output lines
are not used
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Memory: Memory Organization
Noninverting Buffer
 A tri-state device: 0, 1, none
 Output equal input (short circuit), or
none (open circuit)
 A side effect it functions as
amplifier, I.e., in addition to its
switching properties
Inverting Buffer
 Sam as noninverting, with short
circuit when control input is low
(amplifier effect)
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Memory: Memory Chips
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Memory IC is typically organized as a cell matrix
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At each position is a single cell
To get wider output - replicate the matrix
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NxN
128Mbx8b IC may have 8 blocks (individual NxN matrices)
Memory is built out of multiple chips
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256MB DIMM may have 16 128Mx8b ICs
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Eight are read (written) at once delivering 64b of data
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Memory: RAMs and ROMs
 RAMs
– Static – F/F
– Dynamic – transistor + capacitor
– Synchronous
 ROMs
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PROM
EPROM
EEPROM
Flash EPROM – disk replacement potential
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CPU CHIPs and Buses: CPU Chips
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From an internal (to the computer
system) point of view, I/O is
functionally similar to memory
There are two operations read/write
I/O module may control more than
one device.
The interfaces to each external
devices is referred to as port, and
each port is given a unique address
External data path for input output
data with external devices
I/O module may be able to send
interrupt signals to the CPU
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CPU CHIPs and Buses: Computer Buses
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Memory to processor
Processor to memory
I/O to processor
Processor to I/O
I/O to and from Memory
(DMA)
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CPU CHIPs and Buses: Computer Buses
Data Exchange
 Memory to processor
 Processor to memory
 I/O to processor
 Processor to I/O
 I/O to and from Memory (DMA)
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CPU CHIPs and Buses: Computer Buses
Timing Diagram
Signal as a
function of
time
Group of
lines
Binary 1
Binary 0
Leading
edge
Trailing
edge
All lines 0
Time
gap
Not all lines necessarily 0
Time
All lines 0
Cause and effect
dependency
Clock
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CPU CHIPs and Buses: Computer Buses
Bus Types
 Dedicated
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Physical:
 Connected to a subset
of modules
Functional:
 Data bus, Address Bus
Multiplexed:
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Time multiplexing
Address
Data
Time
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CPU CHIPs and Buses: Computer Buses
Bus Configuration
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CPU CHIPs and Buses: Bus Width
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Address lines
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Data lines
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Increases over time
Decrease bus cycle (bus
skew)
Increase data lines
Multiplexed: to allow very
wide buses
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CPU CHIPs and Buses: Bus Clocking
Synchronous Buses
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CPU CHIPs and Buses: Bus Clocking
Asynchronous Buses
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CPU CHIPs and Buses: Bus Arbitration
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More than one module (e.g. CPU and DMA controller ) may need control
of the bus
Only one module may control bus at one time
Needs some form of arbitration
Centralised Arbitration
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Single hardware device controlling bus access (Bus Controller or Arbiter)
May be a separate module or part of CPU or separate
Distributed Arbitration
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Each module may claim the bus
Control logic on all modules
One device is designated as master, which may initiate a data transfer
with some other device (slave)
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CPU CHIPs and Buses: Bus Arbitration
Centralized
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CPU CHIPs and Buses: Bus Arbitration
Decentralized
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CPU CHIPs and Buses
Drawing Conventions
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Thick lines are buses - multiple bits wide
Dotted line is clock
Dashed lines are control signals
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PCI Bus
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Peripheral Component Interconnect
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Start development 1990
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Became standard 1995
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Used in:
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38
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Sun Workstations
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Apple Macintosh
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Wintel PCs
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Compaq Alpha Server
The same peripheral I/O cards may be plugged into many
different computers
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