5
4
3
"CONNECTION"
LD19
2
1
R109
AP1608MGC
A[16..31]
1K
A[16..31]
D[0..7]
5V 3V3
3V3
1
3
IRQW5
7
IRQY9
INT11
13
GPIO68
15
G_TXCLK
17
19
D_REQ
21
23
GPIO50
25
27
GPIO47
29
GPIO44
31
E_RXD1
33
35
37
GPIO92
39
H_TSYNC
41
43
GPIO87
45
B_RXD0
47
D_RXD2
49
51
GPIO100
53
G_RXD0
55
57
GPIO106 59
GPIO97 61
63
HOST_TCK
D
P1
TCK
-12V
GND
INTA#
INTB#
INTC#
BUSMODE1#
+5V
INTD#
PCI-RSVD
GND
3.3Vaux
CLK
GND
GND
GNT#
REQ#
+5V
V(I/O)
AD31
AD28
AD27
AD25
GND
GND
C/BE3#
AD22
AD21
AD19
+5V
V(I/O)
AD17
FRAME#
GND
GND
IRDY#
DEVSEL#
+5V
GND
LOCK#
PCI-RSVD PCI-RSVD
PAR
GND
V(I/O)
AD15
AD12
AD11
AD09
+5V
GND
C/BE0#
AD06
AD05
AD04
GND
V(I/O)
AD03
AD02
AD01
AD00
+5V
GND
REQ64#
P1
3V3 12V
2
G_RSYNC
4
6 IRQX8
C_TSYNC
10
12
14
C_RXD0
16
18
H_RXCLK
20
22 GPIO52
24
26 GPIO86
28
30
D_TXD1
32
34
36 GPIO90
38
40 GPIO65
42 PIB_3V3_PU
44
46 GPIO101
A_RXD0
48
50
E_TXD2
52
H_RXD0
54
56
G_TSYNC
58
60 GPIO105
62
=>
SPI_DOUT
64
1
3
HOST_TMS
5
HOST_TDI
7
9
GPIO103
11
G_TXD0
13
15
PFCRMIISWCLK
17
A_TSYNC
19
21
B_TXD0
23
25
27
D_TXD2
29
31
GPIO104
33
E_RXD2
35
37
E_RXD3
39
41
GPIO84 43
E_TXD1
45
GPIO102_PIB_PU 47
GPIO107 49
C_RSYNC
51
53
C_TXD0
55
A_RSYNC
57
59
G_RXCLK
61
63
!
3V3
P2
+12V
TRST#
TMS
TDO
TDI
GND
GND
PCI-RSVD
PCI-RSVD PCI-RSVD
BUSMODE2# +3.3V
RST#
BUSMODE3#
+3.3V
BUSMODE4#
PME#
GND
AD30
AD29
GND
AD26
AD24
+3.3V
IDSEL
AD23
+3.3V
AD20
AD18
GND
AD16
C/BE2#
GND
PMC-RSVD
TRDY#
+3.3V
GND
STOP#
PERR#
GND
+3.3V
SERR#
C/BE1#
GND
AD14
AD13
M66EN
AD10
AD08
+3.3V
AD07
PMC-RSVD
+3.3V
PMC-RSVD
GND
PMC-RSVD
PMC-RSVD PMC-RSVD
GND
PMC-RSVD
ACK64#
+3.3V
GND
PMC-RSVD
5120527-1
DGND
C
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
G_TXD0
H_TXCLK
G_TXCLK
H_TSYNC
G_TSYNC
H_RXD0
G_RXD0
H_RXCLK
G_RXCLK
H_RSYNC
G_RSYNC
H_TXCLK
HOST_TRSTHOST_TDO
E_RXCLK
GPIO108
GPIO109
F_TXD0
GPIO99
PIB_PD_0R
PIB_PD_0R
F_RXD0
D_TXD3
GPIO98
D_CLKO
D_RXD1
A_RXCLK
GPIO45
GPIO85
GPIO80
GPIO81
A_TXCLK
E_RSYNC
D_RXCLK
E_TSYNC
E_RXD0
E_CLKO
E_TXD3
E_TXD0
C_RXCLK
A_TXD0
D_RXD3
C_TXCLK
D_TSYNC
F_RXCLK
GPIO96
D_TXD0
D_RSYNC
E_TXCLK
PCI_EXTBRD_REQ
D_RXD0
D_TXCLK
SPI_DIN <=
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
5120527-1
DGND
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
P2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
DGND
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
P3
PCI-RSVD
GND
C/BE6#
C/BE4#
V(I/O)
AD63
AD61
GND
AD59
AD57
V(I/O)
AD55
AD53
GND
AD51
AD49
GND
AD47
AD45
V(I/O)
AD43
AD41
GND
AD39
AD37
GND
AD35
AD33
V(I/O)
PCI-RSVD
PCI-RSVD
GND
GND
C/BE7#
C/BE5#
GND
PAR64
AD62
GND
AD60
AD58
GND
AD56
AD54
GND
AD52
AD50
GND
AD48
AD46
GND
AD44
AD42
GND
AD40
AD38
GND
AD36
AD34
GND
AD32
PCI-RSVD
GND
PCI-RSVD
P3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
D0
D2
B_TSYNC
B_TXCLK
E_REQ
D4
D6
D8
D10
B_RXCLK
B_RSYNC
F_TSYNC
F_RSYNC
F_TXCLK
A16
A18
MDC2
SPI_CLK
H_RSYNC
D12
D14
A20
A22
A24
A26
H_TXD0
PCI_EXTBRD_CLK
A28
A30
MDIO
GPIO70
GPL0
GPL1
GPIO4
GPIO6
GPL2
GPL3
GPL4
RD-
GPIO7
GPIO1
RDY-
GPL5
GPIO9
SPI_SEL
GPIO12
!
RESETWR-
WE0LBCTL
SPI_SEL(NU)
GPIO0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
P4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5120527-1
DGND
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
D[0..7]
3V3
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
DGND
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
P4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
D1
D3
D5
D7
D9
D11
D13
D15
D
A17
A19
A21
A23
A25
A27
A29
A31
LCS4LCS5WE1RTS2
CTS2
SIN2
SOUT2
PCI_GNT1
PIB_GND
I2C_DATA
I2C_CLK
5120527-1
DGND
SPI_DIN
SPI_DOUT
SPI_CLK
SPI_SEL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DGND
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
SPI_DIN
SPI_DOUT
SPI_CLK
SPI_SEL
DGND
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
5V
3V3
12V
C
3V3
3V3
5V
5V
12V
12V
"GND" "GND"
TP67
TP66
"5V"
TP68
"3V3"
TP69
"12V"
TP1
DGND
B
B
DFT JTAG INTERCONNECTIONS
HOST TDI
P1
PLD
TDO1
P2
HOST
HOST
HOST
HOST
P3
T1
FRAMER
DS3
FRAMER
TDO2
TCK
TMS
TRST
TDO
P4
Optional (Not populated) components
A
A
Freescale Semiconductor
1, Shenkar st.
Herzelia 46120
Israel
+972-9-9522222
Title
PQ-MDS-T1 (Interconnections1)
5
4
3
2
Size
A3
Document Number
Date:
Sunday, March 05, 2006
Rev
Proto
084-00214-2
Sheet
1
1
of
8
5
4
3
2
1
A[16..31]
D[0..7]
RCLK[1..8]
RSER[1..8]
A3
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
D
D[0..7]
A[16..31]
INT-
INTWRRD-
SW1
1
3
2
4
KT11P2SM-LFS
No_Stuff
DGND
LCS5WRRDRESETAUX_HRST-
LCS5-
"AUX RST"
RESETHOST_TMS
HOST_TCK
HOST_TDI
HOST_TMS
HOST_TCK
HOST_TDI
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
C
B
A4
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
D[0..7]
A[16..31]
INTLCS5WRRDRESETAUX_HRSTHOST_TMS
HOST_TCK
HOST_TDI
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
A2
A
SPI_DOUT
SPI_DIN
SPI_CLK
SPI_SEL
SPI_DOUT
SPI_DIN
SPI_CLK
SPI_SEL
12V
5V
3V3
SPI_DOUT
SPI_DIN
SPI_CLK
SPI_SEL
12V
5V
3V3
DGND
DGND
5
LM_DIN
LM_DOUT
LM_CLK
LM_INTLM_RESET-
LM_DIN
LM_DOUT
LM_CLK
LM_INTLM_RESET-
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
LM_DIN
LM_DOUT
(1.544/2.048MHz)
LM_CLK
LM_INTLM_RESET-
T1_TSSYNCIO
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
RSYNC1
RFYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
A5
CH0_TXSERIN
CH0_TXSYNC
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
CH0_RXSEROUT
CH0_RXSYNC
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
CH0_RXSERCLK
CH0_CLKOUT
CH1_TXSERIN
CH1_TXSYNC
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
CH1_RXSEROUT
CH1_RXSYNC
CH1_RXD0
CH1_RXD1
CH1_RXD2
CH1_RXD3
CH1_RXCLK
CH1_RXSERCLK
CH1_CLKOUT
CH0_TXSERIN
CH0_TXSYNC
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
CH0_RXSEROUT
CH0_RXSYNC
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
CH0_RXSERCLK
CH0_CLKOUT
CH1_TXSERIN
CH1_TXSYNC
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
CH1_RXSEROUT
CH1_RXSYNC
CH1_RXD0
CH1_RXD1
CH1_RXD2
CH1_RXD3
CH1_RXCLK
CH1_RXSERCLK
CH1_CLKOUT
T1_REFCLKIO
T1_CST1_DIGIOEN
T1_TSSYNCIO
T1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
T1_MCLK
T1_TXENABLE
T1_JTRST
T1_INTT1_RESETTDO1
DS3_RESET-
DS3_RESET-
DGND
3V3
DGND
LMA_CARD Connection
4
CONTROL PLD
3V3
DGND
3
DGND
Chassis
T1_FRAMER_I/O
C
B
DGND
Chassis
DS3_FRAMER_I/O
T1_REFCLKIO
D[0..7]
T1_CSA[19..31]
T1_DIGIOEN
T1_WRT1_TSSYNCIO
T1_RDT1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
T1_MCLK
T1_TXENABLE
TDO2
T1_JTRST
HOST_TMS
T1_INTHOST_TCK
T1_RESET- HOST_TRSTTDO1
DGND
3V3
A7
DS3_CSDS3_NIB_MODE
DS3_TXON
DS3_DBENDS3_ALE
DS3_TRST
DS3_INT-
D
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
CHASSIS
DGND
CH1_TXSERIN
CH1_TXSYNC
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
CH1_RXSEROUT
CH1_RXSYNC
CH1_RXD0
CH1_RXD1
CH1_RXD2
CHASSIS
CH1_RXD3
DGND
CH1_RXCLK
CH1_RXSERCLK
CH1_CLKOUT
DGND
DS3_CSDS3_NIB_MODE
DS3_TXON
DS3_DBENDS3_ALE
DS3_TRST
DS3_INT-
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
CH0_TXSERIN
CH0_TXSYNC
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
CH0_RXSEROUT
CH0_RXSYNC
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
CH0_RXSERCLK
CH0_CLKOUT
A6
T1_REFCLKIO
T1_CST1_DIGIOEN
T1_TSSYNCIO
T1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
T1_MCLK
T1_TXENABLE
T1_JTRST
T1_INTT1_RESETTDO1
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
A[19..31]
WRRD-
HOST_TMS
HOST_TCK
HOST_TRST-
HOST_TRST-
3V3
T1_FRAMER_CONTROL
DS3_CSD[0..7]
DS3_NIB_MODE A[17..31]
DS3_TXON
DS3_WRDS3_DBENDS3_RDDS3_ALE
DS3_TRST
TDO2
DS3_INTHOST_TMS
HOST_TCK
DS3_RESET- HOST_TRSTHOST_TDO
DGND
DS3_RDY3V3
A[17..31]
WRRD-
A
Freescale Semiconductor
1, Shenkar st.
Herzelia 46120
Israel
+972-9-9522222
TDO2
HOST_TMS
HOST_TCK
Title
HOST_TDO
0
3V3
HOST_TDO
RDY-
R46
No_Stuff
DS3_FRAMER_CONTROL
2
PQ-MDS-T1 (Interconnections2)
Size
A3
Document Number
Date:
Thursday, March 02, 2006
Rev
Proto
084-00214-2
Sheet
1
2
of
8
5
4
No_Stuff
No_Stuff
No_Stuff
No_Stuff
HOST_TMS
HOST_TCK
TDO1
HOST_TDI
ELJRER12J/GFA
L10
0
R67
No_Stuff
C62
GND
VCC
NC
NC
GND
2
4
6
8
10
TCK
TDO
TMS
NC
TDI
VCC
1
EN/DIS
2
DGND
OSC.
OUT
R68
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
A[16..31]
DGND
ELJRER12J/GFA
L9
3V3
0
Y3
R55
No_Stuff
C63
4
VCC
1
EN/DIS
2
DGND
OSC.
OUT
3
TP34
27
R69
O16.384MJO75E3.31LF
0.1uF
DGND
C
TDM A..H CHANNELS
B
CPU INTERFACE
D[0..7]
3V3
R78
A
10K
LCS5RDWRRESETINT-
AUX_HRST3V3
3V3
DGND
SLIC-SLAC MODULE INTERFACE
DGND
0
R107
J11
D13
J6
TCK
TDO
TMS
0
R103
D4
TDI
D9
D8
1.544MHZ
16.384MHZ
LM_DIN
LM_DOUT
LM_CLK
LM_INTLM_RESET-
2
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
A[16..31]
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
D[0..7]
D7
D6
D5
D4
D3
D2
D1
D0
LCS5RDWRRESETINTAUX_HRST-
E3
L10
R16
K14
J15
P16
K1
R9
P15
K15
K13
N14
C1
T9
R13
K12
J14
T16
B2
M2
B1
A14
J13
M16
J12
T4
P5
N3
T11
N9
K2
G6
G4
G5
J16
M13
H15
N1
N2
P1
M9
M10
F5
L9
R15
K16
N10
R14
H5
R8
T14
L16
R11
P12
F8
N8
P13
L13
M8
N13
J7
E7
C6
B8
F1
E4
B14
L2
D7
C7
D6
B6
F10
A13
A5
D5
D10
F9
D11
D12
B15
D16
F14
E12
C5
A2
E9
E8
N5
D2
A_TXD0
A_TXCLK
A_TSYNC
A_RXD0
A_RXCLK
A_RSYNC
B_TXD0
B_TXCLK
B_TSYNC
B_RXD0
B_RXCLK
B_RSYNC
C_TXD0
C_TXCLK
C_TSYNC
C_RXD0
C_RXCLK
C_RSYNC
D_TXD0
D_TXD1
D_TXD2
D_TXD3
D_TXCLK
D_TSYNC
D_RXD0
D_RXD1
D_RXD2
D_RXD3
D_RXCLK
D_RSYNC
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXCLK
E_TSYNC
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_RXCLK
E_RSYNC
F_TXD0
F_TXCLK
F_TSYNC
F_RXD0
F_RXCLK
F_RSYNC
G_TXD0
G_TXCLK
G_TSYNC
G_RXD0
G_RXCLK
G_RSYNC
H_TXD0
H_TXCLK
H_TSYNC
H_RXD0
H_RXCLK
H_RSYNC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
CS5RDWRRESETINTAUX_HRST-
LM_DIN
LM_DOUT
LM_CLK
LM_INTLM_RESET-
R7
K6
M12
D1
H10
E10
LM_DIN
LM_DOUT
LM_CLK
LM_INTLM_RESETRSRV1
TP18
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
T1_REFCLKIO
T1_CST1_DIGIOEN
T1_TSSYNCIO
T1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
T1_MCLK
T1_TXENABLE
T1_JTRST
T1_INTT1_RESETCH0_TXSERIN
CH0_TXSYNC
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
CH0_RXSEROUT
CH0_RXSYNC
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
CH0_RXSERCLK
CH0_CLKOUT
CH1_TXSERIN
CH1_TXSYNC
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
CH1_RXSEROUT
CH1_RXSYNC
CH1_RXD0
CH1_RXD1
CH1_RXD2
CH1_RXD3
CH1_RXCLK
CH1_RXSERCLK
CH1_CLKOUT
DS3_CSDS3_NIB_MODE
DS3_TXON
DS3_DBENDS3_ALE
DS3_TRST
DS3_INTDS3_RESETRSRV2
RSRV3
RSRV4
RSRV5
PLD
I/O
H3
A7
F7
G1
B16
H6
E1
B7
M1
M5
M4
A15
L5
B12
J3
L1
L12
M7
L8
L7
H11
N7
P7
T7
P11
M11
T10
N11
C10
K11
R10
F16
N16
F13
F12
G11
G13
G14
G16
L15
F2
A6
E5
B4
C4
C3
C11
E6
F15
C16
R12
G12
A1
E16
E13
A10
N15
A11
D15
R1
R6
J1
T5
R5
N6
T6
H2
C13
A12
F3
N4
E11
C12
A4
B13
A16
J5
H14
E2
H13
M6
P4
R4
G2
F4
K3
L4
H4
J4
J2
K5
H1
K4
H7
H16
L14
J10
B11
T13
A9
C15
P2
D3
N12
T12
H12
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
T1_REFCLKIO
T1_CST1_DIGIOEN
T1_TSSYNCIO
T1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
T1_MCLK
T1_TXENABLE
T1_JTRST
T1_INTT1_RESETCH0_TXSERIN
CH0_TXSYNC
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
CH0_RXSEROUT
CH0_RXSYNC
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
CH0_RXSERCLK
CH0_CLKOUT
CH1_TXSERIN
CH1_TXSYNC
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
CH1_RXSEROUT
CH1_RXSYNC
CH1_RXD0
CH1_RXD1
CH1_RXD2
CH1_RXD3
CH1_RXCLK
CH1_RXSERCLK
CH1_CLKOUT
DS3_CSDS3_NIB_MODE
DS3_TXON
DS3_DBENDS3_ALE
DS3_TRST
DS3_INTDS3_RESET-
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
T1_REFCLKIO
T1_CST1_DIGIOEN
T1_TSSYNCIO
T1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
T1_MCLK
T1_TXENABLE
T1_JTRST
T1_INTT1_RESETCH0_TXSERIN
CH0_TXSYNC
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
CH0_RXSEROUT
CH0_RXSYNC
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
CH0_RXSERCLK
CH0_CLKOUT
CH1_TXSERIN
CH1_TXSYNC
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
CH1_RXSEROUT
CH1_RXSYNC
CH1_RXD0
CH1_RXD1
CH1_RXD2
CH1_RXD3
CH1_RXCLK
CH1_RXSERCLK
CH1_CLKOUT
DS3_CSDS3_NIB_MODE
DS3_TXON
DS3_DBENDS3_ALE
DS3_TRST
DS3_INTDS3_RESET-
U2B
T1/E1 FRAMER
4
3
A3
B10
C2
D14
E14
F6
G10
H8
J9
K7
L11
M3
M14
P3
P6
P10
R2
R3
T1
T8
T15
GNDIO1
GNDIO2
GNDIO3
GNDIO4
GNDIO5
GNDIO6
GNDIO7
GNDIO8
GNDIO9
GNDIO10
GNDIO11
GNDIO12
GNDIO13
GNDIO14
GNDIO15
GNDIO16
GNDIO17
GNDIO18
GNDIO19
GNDIO20
GNDIO21
A8
C9
G9
K8
P9
GNDINT1
GNDINT2
GNDINT3
GNDINT4
GNDINT5
DGND
3V3
PLD
POWER
VCCIO17
VCCIO16
VCCIO15
VCCIO14
VCCIO13
VCCIO12
VCCIO11
VCCIO10
VCCIO9
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
B3
B5
C14
E15
F11
G3
G7
G15
H9
J8
K10
L3
L6
M15
P14
T2
T3
VCCINT5
VCCINT4
VCCINT3
VCCINT2
VCCINT1
B9
C8
G8
K9
P8
D
EPM3512AFC256-7N
C
3V3
3V3
DECOUPLING
C76
C73
C100 C97
C112 C75
C77
C94
C71
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C115 C110 C102 C120
10uF
C98
C96
C99
C95
C113 C74
10uF
10uF
10uF
C101 C111 C72
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
Arrange under the CPU package
DGND
DGND
B
DS3/T3 FRAMER
A
PQ-MDS-T1 (CONTROL PLD)
TP35
TP44
TP57
TP43
EPM3512AFC256-7N
5
1
U2A
1_544MHZ
16_384MHZ
DGND
TP33
27
3
O1.544MJO75E3.31LF
0.1uF
1
3
5
7
9
FTS10502LDVP
Y4
4
D
R105
R108
R106
R104
P15
3V3
3V3
3
0
0
0
0
2
Size
A3
Document Number
Date:
Thursday, March 02, 2006
Rev
Proto
084-00214-2
Sheet
1
3
of
8
5
D
ELJRER12J/GFA
L3
3V3
0
C15
U1A
OSC.
4
VCC
1
EN/DIS
2
DGND
27
27
3
HOST_TRST-
Y2
R50
No_Stuff
34_368MHZ
44_736MHZ
3V3
DS3_TRST
4
0
R40
R51
C38
R138
0
R139
No_Stuff
DS3_TDO
DS3_TMS
DS3_TDI
DS3_TCK
EN/DIS
2
DGND
OUT
TP8
3
O44.736MJO75E3.31LF
0.1uF
TP6
TP5
R140 TP2
4.7K TP3
0
OSC.
VCC
1
Y1
Y5
AE4
DS3_TXON
DGND
ELJRER12J/GFA
L7
E3CLK
DS3/SFM_CLK
TXON
W1
W2
W3
W4
GPIO0
GPIO1
GPIO2
GPIO3
AF5
TRST
AB5
AE5
AC5
AD5
TDO
TMS
TDI
TCK
R27
4.7K
DGND
10K
DGND
R35
3V3
No_Stuff
C
Intel asynchronous
mode selected
0
DS3_NIB_MODE
R32
DGND
AB22
AC22
AD22
AC4
PTYPE0
PTYPE1
PTYPE2
NIBBLE_INTF
AD4
AC13
AC17
TESTMODE
Anaio0
Anaio1
DGND
A[17..31]
A[17..31]
No_Stuff
No_Stuff
No_Stuff
No_Stuff
HOST_TMS
HOST_TCK
HOST_TDO
TDO2
0
0
0
0
R38
R36
R48
R49
0
R37
P10
3V3
2
4
6
8
10
DGND
GND
VCC
NC
NC
GND
TCK
TDO
TMS
NC
TDI
FTS10502LDVP
No_Stuff
2
U1B
1
3
5
7
9
0
DS3_TCK
DS3_TDO
DS3_TMS
DS3_TDI
R39
D[0..7]
D[0..7]
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
AB26
AC26
AD26
AB25
AA24
AD25
AC25
AB24
AF25
AE25
AF24
AE24
AD24
AC24
AF23
D7
D6
D5
D4
D3
D2
D1
D0
B
R22
T24
T25
T26
U22
U23
U24
U25
AF22
AB23
AE23
R23
AD23
AC23
U26
AF4
AA26
DS3_DBENDS3_ALE
DS3_CSDS3_INTDS3_RDDS3_WRDS3_RDYDS3_RESET3V3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
DBEN
ALE/AS
CS
INT
RD/DS
WR_R/W
RDY/DTACK
RESET
PCLK
CONTROL
TXUADDR0
TXUADDR1
TXUADDR2
TXUADDR3
TXUADDR4
C8
B8
A8
E9
C9
TXUDATA0
TXUDATA1
TXUDATA2
TXUDATA3
TXUDATA4
TXUDATA5
TXUDATA6
TXUDATA7
TXUDATA8
TXUDATA9
TXUDATA10
TXUDATA11
TXUDATA12
TXUDATA13
TXUDATA14
TXUDATA15
C3
B2
A1
A2
B3
A3
D5
C4
B4
A4
C5
B5
A5
C6
B6
A6
TXMOD
TXUCLK
TXUSOC
TX_TSX/PSOF
TXUCLKO
TXUCLAV
TXUPRTY
TXUEN
TXPERR
TXPEOP
A11
B10
B7
B11
A7
B9
C7
D7
D11
C11
RXADDR0
RXADDR1
RXADDR2
RXADDR3
RXADDR4
B14
C14
A15
B15
C15
RXUDATA0
RXUDATA1
RXUDATA2
RXUDATA3
RXUDATA4
RXUDATA5
RXUDATA6
RXUDATA7
RXUDATA8
RXUDATA9
RXUDATA10
RXUDATA11
RXUDATA12
RXUDATA13
RXUDATA14
RXUDATA15
A17
B17
C17
E17
A18
B18
C18
A19
B19
C19
D19
A20
B20
C20
A21
B21
RXMOD
RXUPRTY
RXPEOP
RXPDVAL
RXUEN
RXUSOC
RXUCLK
RXPERR
RX_TSX/PSOF
RXUCLAV
RXUCLKO
A10
A12
E6
E7
E8
E10
E11
E12
E14
E15
E16
E18
E19
E20
F5
F22
L5
L11
L12
L13
L14
L15
L16
L22
M13
M14
N13
N14
P13
P14
R13
R14
T5
T11
T12
T13
T14
T15
T16
T22
AA5
AA22
AB6
AC6
AC18
AD9
AD21
AE8
AE20
AE22
AF7
AF8
AF12
AF16
AF19
AF20
B13
B16
E13
A9
C16
A16
B12
A13
C13
D15
A14
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
AD13
AD17
JAAGND1
JAAGND2
AB14
REFAGND
AE12
AE16
RXAGND1
RXAGND2
AC10
AC14
TXDGND1
TXDGND2
AF11
AF15
TXAGND1
TXAGND2
3V3
XRT79L72IB-F
1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD45
VDD46
VDD43
JAAVDD1
RXAVDD1
D6
D8
D9
D10
D12
D13
D14
D16
D17
D18
D20
L4
L23
M11
M12
M15
M16
N11
N12
N15
N16
P11
P12
P15
P16
R11
R12
R15
R16
T4
T23
AA4
AA23
AB8
AB18
AB20
AC7
AC19
AE9
AE21
AF6
AF9
AF18
AF21
AF13
AE13
AB12
JAAVDD2
RXAVDD2
VDD44
AE17
AB16
AF17
REFAVDD
AB13
RXAVDD3
RXAVDD4
C10
C12
TXDVDD1
TXAVDD3
AF10
AC11
TXDVDD2
TXAVDD4
AF14
AC15
3V3
DECOUPLING
C23
C57
C24
C28
C42
C25
C55
C41
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C36
C46
C32
C43
C60
C51
C37
C17
C22
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C26
C21
C48
C44
C39
C18
C58
C19
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
C47
C45
C16
C59
C53
C50
C27
C56
C52
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
C54
C49
C14
C40
47uF
47uF
47uF
47uF
Arrange under the CPU package
in accordance with drawing
DGND
DECOUPLING
C30
ELJRER12J/GFA
L4
C31
0.1uF 0.1uF
C34
ELJRER12J/GFA
L6
C33
0.1uF 0.1uF
ELJRER12J/GFA
L5
C20
ELJRER12J/GFA
L8
0.1uF
C61
ELJRER12J/GFA
L1
0.1uF
POWER
D
U1C
3V3
TP7
OUT
O34.368MJO75E3.31LF
0.1uF
3V3
3
Y1
R33
No_Stuff
4
C10
A24
B23
B24
B26
C22
C23
C25
C26
D1
D2
D3
D24
D25
D26
E1
E4
E23
E24
F4
F23
G4
G5
G22
G23
G24
G25
H1
H2
H3
H4
H5
H25
H26
J1
K3
K4
K5
K23
K24
K25
K26
L1
L2
L3
L24
L25
L26
M22
M23
N5
P1
P2
P3
P4
P5
P22
P23
P24
P25
P26
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60
NC
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
NC73
NC74
NC75
NC76
NC77
NC78
NC79
NC80
NC81
NC82
NC83
NC84
NC85
NC86
NC87
NC88
NC89
NC90
NC91
NC92
NC93
NC94
NC95
NC96
NC97
NC98
NC99
NC100
NC101
NC102
NC103
NC104
NC105
NC106
NC107
NC108
NC109
NC110
NC111
NC112
NC113
NC114
NC115
NC116
NC117
NC118
NC119
NC120
R3
R4
R5
R24
R25
R26
U1
U2
V1
V2
V3
V4
V5
V26
W5
W22
W23
W24
Y2
Y3
Y4
Y24
Y25
Y26
AA25
AB2
AB3
AB4
AB7
AB9
AB10
AB11
AB15
AB17
AB19
AB21
AC1
AC3
AC8
AC9
AC20
AC21
AD1
AD3
AD6
AD7
AD8
AD18
AD19
AD20
AE1
AE3
AE6
AE7
AE18
AE19
AE26
AF2
AF3
AF26
C
B
XRT79L72IB-F
C11
0.1uF 0.1uF
C12
C13
0.1uF
0.1uF
ELJRER12J/GFA
L2
Arrange under the CPU package
in accordance with drawing
XRT79L72IB-F
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
A
A
PQ-MDS-T1 (DS3/T3 FRAMER_CONTROL)
5
4
3
2
Size
A3
Document Number
Date:
Thursday, March 02, 2006
Rev
Proto
084-00214-2
Sheet
1
4
of
8
5
4
3
2
1
D
D
For “Nibble-Parallel Mode” operation,
sample the data on the “RxNib[3:0]”
output pins, upon the
RISING
edge of this clock signal.
Remove to use in
"Slave Mode"
R127
10K
10K
R34
TP11
DGND
N2
J3
J4
K1
J5
AC12
U3
J2
8
TP9
470
G1
F3
E5
F2
B1
D4
C2
C1
1
P6
Chassis
"CH0_RC"
RXSER1
RXFRAME1
J22
H22
H23
H24
K22
RXNIB1_0
DMO1
RXNIB1_1
RXLOS1
RXNIB1_2
RXNIB1_3
RXPRED1
RXCLK1/RXNIBCLK1 RXPOOF1
RXPLOF1
RXOUTCLK1
TXPOHFRAME1
TXPOHCLK1
TXOHIND1
TXGFCCLK1
TXOH1
TXOHINS1
RXPOHFRAME1
TXOHENABLE1 RXCELLRXED1
TXOHFRAME1
RXGFCMSB1
TXOHCLK1
RXGFCCLK1
RXGFC1
RXOHIND1
RXOH1
RXOHENABLE1
CLKOUT1
RXOHFRAME1
TXINCLK1
RXOHCLK1
TAISEN1
CH1_RXD0
CH1_RXD1
CH1_RXD2
CH1_RXD3
CH1_RXCLK
(Loop timing mode only-rising edge)
CH1_RXSERCLK
C29
AP1608SECK
For “Serial Mode” operation,
sample the data on the “RxSer”
output pin, upon the FALLING
edge of this clock signal.
0.1uF
DGND
CH0_CLKOUT
M25
Y22
W26
M24
D23
A26
TP12
For “Nibble-Parallel Mode” operation,
sample the data on the “RxNib[3:0]”
output pins, upon the RISING
edge of this clock signal.
E3_34.368/DS3_44.736MHz
TP15
TP45
C5
1000pF
CHANNEL0
XRT79L72IB-F
DGND
J23
DGND
Remove to use in
"Slave Mode"
Chassis
J25
E26
F26
F24
F25
TXNIB1_0
TXNIB1_1
TXNIB1_2
TXNIB1_3
TXNIBCLK1
TXNIBFRAME1
31.6
TRING1
AE14
RTIP1
AD16
RRING1
R8
31.6
AC16
N26
E25
142147
1
3
4
16
13
14
15
7
5
6
10
12
11
499
A25
D21
A22
B22
A23
R3
R4
9
1
T3023NL
C4
0.01uF
P8
142147
Chassis
"CH1_RC"
470
C24
B25
C21
C3
0.01uF
2
R10
D22
E22
E21
P7
499
8
TP14
1
5
4
3
2
CH1_RXSEROUT
CH1_RXSYNC
J24
J26
LD1
DGND
K2
U4
AE2
V25
V24
V23
V22
N22
N23
"CH1_TR"
T2
R7
5
4
3
2
C1
0.01uF
142147
T3023NL
R9
E2
F1
E3
5
4
3
2
9
R2
CH1_TXD0
CH1_TXD1
CH1_TXD2
CH1_TXD3
CH1_TXNIBCLK0
CH1_TXNIBFRAME
R30
274
R31
No_stuff
R43
499
TTIP1
AD14
274
R45
10
12
11
AE15
AD15
C
37.4
15
7
5
6
MTIP1
MRING1
37.4
2
31.6
R1
TXSER1
TXFRAME1
TXFRAMEREF1
"CH1_LOSS"
RRING0
C2
0.01uF
R44
R1
AD2
AC2
R2
G2
G3
TP10
AD12
P5
10K
CH0_RXSERCLK
For “Serial Mode” operation,
sample the data on the “RxSer”
output pin, upon the FALLING
edge of this clock signal.
M5
AE10
RTIP0
1
499
R41
RXNIB0_0
DMO0
RXNIB0_1
RXLOS0
RXNIB0_2
RXNIB0_3
RXPRED0
RXCLK0/RXNIBCLK0 RXPOOF0
RXPLOF0
RXOUTCLK0
TXPOHFRAME0
TXPOHCLK0
TXOHIND0
TXGFCCLK0
TXOH0
TXOHINS0
RXPOHFRAME0
TXOHENABLE0 RXCELLRXED0
TXOHFRAME0
RXGFCMSB0
TXOHCLK0
RXGFCCLK0
RXGFC0
RXOHIND0
RXOH0
RXOHENABLE0
CLKOUT0
RXOHFRAME0
TXINCLK0
RXOHCLK0
TAISEN0
TRING0
R6
16
13
14
37.4
RXSER0
RXFRAME0
M4
M3
M2
M1
N4
CH0_RXD0
CH0_RXD1
CH0_RXD2
CH0_RXD3
CH0_RXCLK
31.6
R42
CH0_RXSEROUT
CH0_RXSYNC
N1
N3
TXNIB0_0
TXNIB0_1
TXNIB0_2
TXNIB0_3
TXNIBCLK0
TXNIBFRAME0
1
3
4
M26
N24
W25
CH1_TXSERIN
CH1_TXSYNC
TP13
142147
T1
R5
37.4
AB1
AA3
AA2
AA1
T2
T1
274
R28
No_stuff
No_stuff
U1E
"CH0_TR"
R47
TTIP0
AD10
No_stuff
274
R29
10K
AE11
AD11
CH0_TXD0
CH0_TXD1
CH0_TXD2
CH0_TXD3
CH0_TXNIBCLK0
CH0_TXNIBFRAME
(Loop timing mode only-rising edge)
B
MTIP0
MRING0
"CH0_LOSS"
C
TXSER0
TXFRAME0
TXFRAMEREF0
5
4
3
2
U1D
T3
U5
AF1
CH0_TXSERIN
CH0_TXSYNC
TP4
LD2
C35
AP1608SECK
DGND
0.1uF
DGND
E3_34.368/DS3_44.736MHz
G26
N25
Y23
CH1_CLKOUT
TP16
CHANNEL1
XRT79L72IB-F
DGND
DGND
DGND
B
DGND
CHASSIS
Chassis
A
A
PQ-MDS-T1 (DS3/T3 FRAMER_INTERFACE)
5
4
3
2
Size
A3
Document Number
Date:
Thursday, March 02, 2006
Rev
Proto
084-00214-2
Sheet
1
5
of
8
5
4
3
2
1
Standard Legerity UVB Connector
D
3V3
!
12V
R146
10K
SPI_DOUT
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17
A18
B18
A19
B19
A20
B20
A21
B21
A22
B22
A23
B23
A24
B24
A25
B25
S1
DIN =>
DCLK/S0
SPI_CLK
C
<=
SPI_DIN
DOUT
3V3
R102
"TS_CNTR"
TP65
LM_DOUT
LM_DIN
B
10K
TSCA_N
DXA/DU
DRA/DD
3V3
3V3
5V
5V
12V
12V
D
3V3
R147
10K
P14
CS0_N
SPI_SEL
3V3 5V 12V
D1
C1
D2
C2
D3
C3
D4
C4
D5
C5
D6
C6
D7
C7
D8
C8
D9
C9
D10
C10
D11
C11
D12
C12
D13
C13
D14
C14
D15
C15
D16
C16
D17
C17
D18
C18
D19
C19
D20
C20
D21
C21
D22
C22
D23
C23
D24
C24
D25
C25
INT0_N/S2
RST_N
!
P14
TOP VIEW
D1
LM_INT-
C1
B1
A1
LM_RESET-
C
U4
Legerity Line Module
Le71HR0826
Le71HR0826
PCLK/DCL
FS/FSC
LM_CLK
T1_TSSYNCIO
B
D25 C25 B25 A25
FOLC12502SQLC
P11
1
2
3
4
SLW10201SD
P12
2
4
1
3
DGND
SLW10201SD
DGND
DGND
DGND
A
A
PQ-MDS-T1 (LM CARD CONNECTION)
5
4
3
2
Size
A3
Document Number
Date:
Thursday, December 29, 2005
Rev
Proto
084-00214-2
Sheet
1
6
of
8
5
4
3
0
T1_JTRST
1
R84
0
HOST_TRST-
2
R77
No_Stuff
No_Stuff
No_Stuff
No_Stuff
No_Stuff
HOST_TMS
HOST_TCK
TDO2
TDO1
D
R58
R54
R52
R62
2
4
6
8
10
DGND
GND
VCC
NC
NC
GND
TCK
TDO
TMS
NC
TDI
FTS10502LDVP
No_Stuff
R94
1
3
5
7
9
0
R53
0
R60
L5
F5
J4
K4
H4
10K
T7
M8
R7
R9
M13
CSB
RDB/DSB
WRB/RWB
INTB
BTS
B7
J12
A7
D8
E8
L12
P13
N13
L13
MCLK
RESETB
REFCLKIO
DIGIOEN
BPCLK
RSYSCLK
TSYSCLK
TSSYNCIO
TXENABLE
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
C10
A10
B10
F9
E9
D9
C9
A9
B9
F8
B8
A8
C8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D7
D6
D5
D4
D3
D2
D1
D0
N8
L9
P8
T8
R8
M9
N9
T9
D0
D1
D2
D3
D4
D5
D6
D7
No_Stuff
0
R95
T1_MCLK
T1_RESETT1_REFCLKIO
T1_DIGIOEN
T1_BPCLK
T1_RSYSCLK
T1_TSYSCLK
DGND
T1_TSSYNCIO
R96
R63
T1_TXENABLE
A[19..31]
1M
1M
C
DGND
D[0..7]
JTRST
JTCLK
JTDO
JTMS
JTDI
R101
3V3
T1_CST1_RDT1_WRT1_INT-
3V3
Intel Bus Timing
Selected
3V3
U3A
P13
3V3
10K
0
0
0
0
H12
H13
SCANENABLE
SCANMODE
J5
J6
J10
J11
DVSSIO1
DVSSIO2
DVSSIO3
DVSSIO4
J9
J8
J7
DVSSLIU
DVSSPP
ACVSS
B
3V3
3V3
CONTROL
DGND
DGND
DGND
G8
G6
G7
G5
G12
G11
G10
G9
ARVDD1
ARVDD2
ARVDD3
ARVDD4
ARVDD5
ARVDD6
ARVDD7
ARVDD8
D1
E1
M1
N1
N16
M16
E16
D16
ATVDD1
ATVDD2
ATVDD3
ATVDD4
ATVDD5
ATVDD6
ATVDD7
ATVDD8
B1
G1
K1
R1
R16
K16
G16
B16
DVDDIO1
DVDDIO2
DVDDIO3
DVDDIO4
H5
H6
H10
H11
DVDDPP
DVDDLIU
ACVDD
H8
H9
H7
DVSS1
DVSS2
DVSS3
DVSS4
DVSS5
DVSS6
DVSS7
DVSS8
K8
K7
K5
K6
K11
K12
K10
K9
ARVSS1
ARVSS2
ARVSS3
ARVSS4
ARVSS5
ARVSS6
ARVSS7
ARVSS8
D2
E2
M2
N2
N15
M15
E15
D15
ATVSS1
ATVSS2
ATVSS3
ATVSS4
ATVSS5
ATVSS6
ATVSS7
ATVSS8
B2
G2
K2
R2
R15
K15
G15
B15
C
B
3V3
DECOUPLING
C87
C89
C65
C66
D
DGND
DS26528
3V3
C85
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
DVDD6
DVDD7
DVDD8
C80
C106 C108 C67
C68
C82
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A
C83
C86
C88
C90
C84
C79
C81
C105 C107 C91
C114
C121
10uF
10uF
A
C92
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
Arrange under the CPU package
DGND
DGND
PQ-MDS-T1 (T1_FRAMER_CONTROL)
5
4
3
2
Size
A3
Document Number
Date:
Thursday, March 02, 2006
Rev
Proto
084-00214-2
Sheet
1
7
of
8
3
DGND
AP1608SYCK
D3
330
RLF_LTC1
TP27
TP26
TSER2
TCLK2
TSYNC2
TSIG2
TCHBK_CK2
TP39
TP30
TP28
D6
G4
B6
E6
B5
C6
RSER2
RCLK2
RSYNC2
RSIG2
RCHBK_CK2
RM_RFSYNC2
R64
R73
RSER2
RCLK2
RSYNC2
"CH.2"
C
1M
1M
AP1608MGC
LD6
"RLF2"
DGND
AP1608SYCK
F3
330
CH.1
R130
E3
TRINGA2
TRINGB2
TTIPA2
TTIPB2
TP46
TP42
TSER3
TCLK3
TSYNC3
TSIG3
TCHBK_CK3
TP41
TP61
TP47
N4
L4
N5
M5
L6
P4
RSER3
RCLK3
RSYNC3
RSIG3
RCHBK_CK3
RM_RFSYNC3
R93
R85
RSER3
RCLK3
RSYNC3
"CH.3"
1M
1M
B
AP1608MGC
LD8
"RLF3"
DGND
AP1608SYCK
L3
330
M3
330
TRINGA3
TRINGB3
TTIPA3
TTIPB3
TP56
TP64
TSER4
TCLK4
TSYNC4
TSIG4
TCHBK_CK4
TP48
TP63
TP55
N6
M4
T6
R5
T5
P6
RSER4
RCLK4
RSYNC4
RSIG4
RCHBK_CK4
RM_RFSYNC4
R89
R81
RSER4
RCLK4
RSYNC4
"CH.4"
1M
1M
AP1608MGC
LD10
"RLF4"
A
DGND
AP1608SYCK
P3
330
N3
R123
330
DS26528
9
T4E
24
TRA2
24
10
23
TX1475NL
R116
TTA2
MEC112002SDRA1SL
P9
11
T4F
22
RR2
R117
F1
12
0
R76
R82
61.9
61.9
21
TX1475NL
RT2
J3
K3
TX 1:2
R120
7
0
C117
R121
J1
J2
T4D
26 TRA3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
22
T3F
25
TX1475NL
5
T4C
28
RT5
RR5
RT6
RR6
R26
0
21
R16
12
TX1475NL
TTA6
TRA6
TTA7
TRA7
RT7
RR7
61.9
C103
0.1uF
26
T3D
R23
7
6
0
0
C8
8
TX1475NL
R24
0
TTIPA4
TTIPB4
RR3
28
T3C
R13
5
F15
27
TX1475NL
RT3
27
R14
6
TX1475NL
F16
0
R79
61.9
61.9
TX 1:2
1
0
T4A
TRA4
TRA8 32
CH.4
1
2
31
TX1475NL
TTA4
TTA8
R112
3
T4B
31
2
TX1475NL
R22
0
30
RR4
RR8
30
T3B
3
R11
C15
0
4
29
TX1475NL
RT4
RT8
29
4
TX1475NL
R12
C16
0
R92
R91
R71
R70
61.9
61.9
61.9
61.9
DGND
C109
0.1uF
DGND
DGND
A15
A16
0
R113
TRINGA7
TRINGB7
TTIPA7
TTIPB7
RRING7
AP1608MGC
R136 "RLF5" LD12
330
TSER6
TCLK6
TSYNC6
TSIG6
TCHBK_CK6
L11
N11
T12
R12
P11
RSER6
RCLK6
RSYNC6
RSIG6
RCHBK_CK6
RM_RFSYNC6
M12
J13
P12
R13
T13
N12
RLOS_RSGF6
L14
RLF_LTC6
TSER6
TCLK6
TSYNC6
RSER6
RCLK6
RSYNC6
TP49
TP52
TP50
"CH.6"
C
R137 "RLOS6" LD13
330
AP1608MGC
LD14
R141 "RLF6"
M14
330
DGND
AP1608SYCK
F10
E10
B11
A11
D10
TP23
TP17
RSER7
RCLK7
RSYNC7
RSIG7
RCHBK_CK7
RM_RFSYNC7
B12
F13
C11
A12
C12
D11
TP21
TP20
TP22
RLOS_RSGF7
F14
CH.7
RLF_LTC7
E14
TSER7
TCLK7
TSYNC7
RSER7
RCLK7
RSYNC7
"CH.7"
R142 "RLOS7" LD15
330
AP1608MGC
R143 "RLF7" LD16
330
DS26528
AP1608SYCK
U3I
TRINGA8
TRINGB8
TTIPA8
TTIPB8
RRING8
TSER8
TCLK8
TSYNC8
TSIG8
TCHBK_CK8
D12
B13
A13
C13
E11
TP19
TP24
RSER8
RCLK8
RSYNC8
RSIG8
RCHBK_CK8
RM_RFSYNC8
F11
E13
D13
F12
G13
E12
TP37
TP40
TP36
RLOS_RSGF8
C14
RLF_LTC8
D14
RSER8
RCLK8
RSYNC8
"CH.8"
R144 "RLOS8" LD17
330
RTIP8
CH.8
TSER8
TCLK8
TSYNC8
AP1608MGC
R145 "RLF8" LD18
330
DS26528
DGND
AP1608SYCK
DGND
PQ-MDS-T1 (T1_FRAMER_I/O)
2
B
DGND
Size
A3
Document Number
Date:
Tuesday, December 06, 2005
Rev
Proto
084-00214-2
Chassis
3
R99
DGND
TP51
TP53
TSER7
TCLK7
TSYNC7
TSIG7
TCHBK_CK7
DGND
4
D
AP1608SYCK
C64
0.1uF
DGND
CHASSIS
5
R100
330
RTIP7
RX 1:1
0
P1
A14
B14
0
560pF
560pF
0
P2
R21
C7
RX 1:1
RRING4
T3A
C116
R111
61.9
"CH.5"
R135 "RLOS5" LD11
U3H
DGND
TX 1:2
32
CH.6
R72
C78
0.1uF
R110
T1
T2
H15
H16
RLF_LTC5
N14
TP58
TP54
TP59
DS26528
RX 1:1
DGND
R83
DGND
R3
T3
G14
H14
P14
RTIP6
DGND
TX 1:2
25
Chassis
R86
61.9
C93
0.1uF
TRINGA4
TRINGB4
RRING6
0
R115
TRINGA6
TRINGB6
L15
R80
RLOS_RSGF5
RSER5
RCLK5
RSYNC5
U3G
TTIPA6
TTIPB6
L16
M11
K13
R10
R11
T11
P10
TSER5
TCLK5
TSYNC5
TP60
TP62
DS26528
J15
J16
0
0
L1
0
0
TTA3
DGND
J14
K14
R15
11
560pF
8
R114
L2
9
560pF
0
CH.5
DGND
R25
RSER5
RCLK5
RSYNC5
RSIG5
RCHBK_CK5
RM_RFSYNC5
RTIP5
RX 1:1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
0
T3E
M10
L10
N10
T10
P9
1M
P16
0
C9
560pF
23
10
TX1475NL
560pF
0
61.9
RLOS_RSGF4
RLF_LTC4
R18
14
TX1475NL
TX 1:2
C118
F2
CH.3
RRING5
C104
0.1uF
R122
R90
RTIP4
R134
19
TX 1:2
LD9
"RLOS4" R133
RT1
RX 1:1
RRING3
P15
61.9
U3E
N7
L8
M7
R6
P7
R17
13
61.9
H1
H2
DS26528
TSER4
TCLK4
TSYNC4
19
TX1475NL
C70
0.1uF
RLOS_RSGF3
RLF_LTC3
T3G
61.9
DGND
RTIP3
R132
20
61.9
LD7
"RLOS3" R131
RR1
R88
0
CH.2
TTIPA5
TTIPB5
R87
U3D
TSER3
TCLK3
TSYNC3
20
RX 1:1
RRING2
T15
T16
0
RX 1:1
R74
G3
H3
DS26528
R4
P5
M6
T4
L7
R20
C69
0.1uF
RLOS_RSGF2
RLF_LTC2
T4G
16
TX1475NL
R75
DGND
RTIP2
330
14
0
LD5
"RLOS2" R129
13
17
0
R119
C1
U3C
TSER2
TCLK2
TSYNC2
TTA5
0
DS26528
E7
D7
F7
A6
C7
TTA1
TSER5
TCLK5
TSYNC5
TSIG5
TCHBK_CK5
1M
RLOS_RSGF1
RTIP1
R128
17
TX1475NL
TRINGA5
TRINGB5
R98
R118
0
560pF
16
R14
T14
R97
"RLF1"
C3
330
15
560pF
0
C2
R19
C6
RX 1:1
RRING1
18
T3H
1M
1M
1M
AP1608MGC
LD4
18
TRA5
C119
R125
A1
A2
U3F
TX 1:2
TRA1
1M
0
LD3
"RLOS1" R126
15
T4H
R59
TTIPA1
TTIPB1
R124
R61
TP38
TP32
TP25
RSER1
RCLK1
RSYNC1
RSIG1
RCHBK_CK1
RM_RFSYNC1
A3
B3
1M
"CH.1"
E5
F4
A4
D4
E4
C4
TX 1:2
TRINGA1
TRINGB1
1M
R65
D
R66
RSER1
RCLK1
RSYNC1
TSER1
TCLK1
TSYNC1
TSIG1
TCHBK_CK1
R57
TP31
TP29
F6
C5
B4
D5
A5
1
R56
U3B
TSER1
TCLK1
TSYNC1
2
1M
4
1M
5
Sheet
1
8
of
8
A