UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on September 25, 2001 by Hanching Fuh ([email protected])
Borivoje Nikolic
Homework #3: CMOS Inverters and Design Rules
EECS 141
Solutions
Problem #1
Consider the inverter circuit shown in Figure 1a with an ideal square-wave input. Assume that short-channel
effects are negligible – meaning VDSAT >> VDS, VGS-VT.
!VDD = 5.0V
Vt = 0.7V
Vm = Vdd/2 = 2.5V
LM1, M2 = 0.5um
WM1 = 0.75 um
WM2 = 1.0 um
Ldiff = 0.625 um
kn = 100uA/V2
 = 0 V-1
 = 0.2 V1/2
F = -0.3V
Reference:
Table 3.5 (Draft Chapters)
Figure 1a
Draft Chapter 5
(For your own edification, a node preceded by a “!” (i.e. !V DD and !GND) denotes a global node in a netlist.)
Using the information above and references in the text, determine the following:
a)
Find VOH and VOL. Clue: both the load and driver transistors are NMOS, so don’t say 5.0V and 0V!
VOH
As you see, since the pull-up is an NMOS that is diode connected (VGS = VDS), this is an unconventional
inverter. An NMOS, as you probably found out, makes a poorer pull-up than a PMOS does! Since M1
is diode connected, it is either saturated or in cutoff. To pull the output to the highest possible voltage
(the definition of VOH), M1 must be on. This occurs when M1 is “barely” turned on…
VGS = Vt → VDD-VOH = Vt
Don’t forget BODY EFFECT!
Vt  Vto   ( | 2F | VSB  | 2F | )
In this case, VSB = VOH
Solving the equation VOH = VDD-Vt iteratively, you obtain VOH = 4.025 V
VOL
Note that in our NMOS-only inverter, unlike with a CMOS implementation, the load transistor M1 is
ALWAYS conducting. Once Vout = VOL for some time, the load capacitor is fully charged and thus the
currents equate, ID1 = ID2. Now we must figure out which regions M1 and M2 are in.
M1:
VDS1 = VDD - VOL
VDS,SAT1 = VGS - Vt = VDD - VOL - Vt
VDS1 > VDS,SAT1 → M1 saturated
M2:
VDS2 = VOL
VDS,SAT2 = VGS - Vt = VDD - Vt
VDS2 < VDS,SAT2 → M2 linear
Note that VDS,SAT is the long channel definition and not velocity saturated!
Now solve by setting currents equal
ID1 = ½ k’ (W/L)1 (VDD-VOL-Vt)2 = k’(W/L)2 ((VDD-Vt)*VOL-VOL2/2) = ID2
VOL = 1.05V
The above solution assumes no body effect on M1. This is not completely true (but since V SB = VOL,
which is low it is not a bad assumption). With body effect taken into account, VOL = 1.008 V. Pretty
darn close, eh?
b) Calculate tpLH and tpHL. This will require you to find a Req and Ceq in each case.
To calculate both tpLH and tpHL, you use the equation t = 0.69ReqCeq. This involves finding the Req and
Ceq, which are different on the H→L and L→H transitions. You can do a complicated integral, but for
our first order approximations, you can find the resistance and capacitance at the start and end of a
transition and average them.
tpHL
The H → L transition begins at Vout = VOH and ends at Vout = VM = 2.5 V in this problem
Let’s find the equivalent resistance at the start and end points respectively. In both cases, we model M1
and M2 as resistors. Let’s call them Rup and Rdown, respectively. Since they are both attached to DC
sources (VDD and ground), they are attached to AC ground and thus Req(start or end) = Rup || Rdown.
How do we calculate the equivalent resistances? Remember V = IR!
Rdown (M2):
VDS @ beginning = VOH = 4.025 V
IDS @ beginning = ½ k’ (W/L) 2 (VDD-Vt)2 = ½*100µA/V2*2*(5V-0.7V)2 = 1.85 mA
VDS @ end = VM = 2.5V → this is given in the statement of the problem
VDS,M2 = 2.5V < VDS,SAT,M2 = VDD - Vt = 4.3V → linear
IDS @ end = k’(W/L)2[(VDD-Vt)VM-VM2/2] = 100µA/V2*2[(5V-0.7V)*2.5V-(2.5V)2/2]
= 1.525 mA
Rdown,begin = 2.18kΩ
Rdown,end = 1.64kΩ
Similarly, for Rup (M1):
VDS @ beginning = VDD -VOH = 0.975 V
IDS @ beginning = 0 mA! because transistor is off (with the help of our friend body effect)
VDS @ end = VDD - VM = 2.5V → we know M1 is always saturated if on!
IDS @ end = ½ k’(W/L)1(VDD-VM-Vt)2 = ½*100µA/V2*1.5*(5V-2.5V-Vt)2
= 0.193 mA, where VSB for M1 = VM = 2.5V
Rup,begin = ∞
Rup,end = 13kΩ
½ (Rup,begin || Rdown,begin + Rup,end || Rdown,end) = Req = 1.82 kΩ
To solve for the load capacitance, we consider the signal path and count the capacitances in the path.
For tPHL, the path from Vout to GND hits three parasitic load capacitances: Csb1, Cdb2, and Csb2, as well as
the CL = 50fF of the next stage. You can solve for the parasitic junction capacitances with
Csb = (Keq,nAswCjo + Keq,swPswCjsw) where Asw = W*Ldiff and Psw = W+2Ldiff
There is an example of this in ex. 3.5 and table 3.5 of the notes. For the purposes of this homework
solution, I will skip it. It adds a lot of work and only comes out to approximately 4 fF total for all
three parasitic junction capacitances listed above. Since C L = 50fF >> 4fF, the 4fF makes a very
small difference. You will not be penalized if you stated this assumption and did not calculate the
junction capacitances. Ceq ≈ 50fF. Sorry for all the torture if you went through all the capacitance
calculation! We’ll buy you all donuts sometime (if we can remember).
tPHL = 0.69ReqCeq = 62.8 ps
tPLH
Thankfully, tPLH is easier to calculate because Rdown = ∞ at the start and end of the transition because
VGS, M2 = 0V < Vt, meaning it is always off. What are the start and end points of the transition? V OL
and VM! 
Rup (M1):
VDS @ beginning = VDD -VOL = 5.0V - 1.05V = 3.95V
IDS @ beginning = ½ k’(W/L)1(VDD-VOL-Vt(VSB=VOL))2 =0.743 mA
The notation Vt(VSB=VOL) indicates Vt at a given source-body voltage
VDS @ end = VDD - VM = 2.5V
IDS @ end = ½ k’(W/L)1(VDD-VM-Vt(VSB=VM))2 = ½*100µA/V2*1.5*(5V-2.5V-0.897V)2
= 0.193 mA, where VSB for M1 = VM = 2.5V
Rup,begin = 5.32 kΩ
Rup,end = 13 kΩ
Req = ½ (Rup,begin + Rup,end) = 9.16 kΩ
As with above, you can calculate the capacitances in the signal path from V out to VDD. In this case, the
capacitances are Cdb1, Csb1, Cdb2 and the CL. You can calculate it (we won’t here!) and it is about 3fF.
Using the same assumption above, we will again say 50fF is much larger than the junction parasitics.
Thus,
tPLH = 0.69ReqCeq = 316 ps
c)
The 50fF load capacitor drawn in the diagram, rather than being an explicit capacitor, actually models
the parasitic capacitance. List at least two sources of this parasitic capacitance, as well as two things a
design and/or process engineer can do to alter/reduce it. (Hint: What capacitances are inherently
present at the output node of this stage? These will be the parasitics!)
Sources of parasitic capacitance that CL can model: junction capacitances, input (gate) capacitance of
following stage, and wire capacitance
Ways to alter the parasitic capacitances: resize next stage, resize current stage, shorten wires, or change
the doping of the junctions
d) Find the static power dissipation for –
i. Vin = 0.0V ii. Vin = 5.0
Assuming no leakage current,
i. When Vin = 0.0V, M2 is off and no path exists between VDD and GND
P=0W
ii. M1 and M2 are both on
P = IV = ID*VDD = ½ k’(W/L)2(VDD-Vt)2 *VDD= ½ (100µA/V2)*2*(5.0V-0.7V)2 *5.0V
= 9.2 mW
Problem #2
a)
It is always good to get a feel for design rules in a layout editor. Fire up max with the mmi25 (0.25 um)
technology file (this is the default setup). Place a minimum sized NMOS transistor and examine the
dimensions. The layers are listed and shown below in Figure 2a. Determine and list the following:
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Please list the design rules you come across that lead to your results.
*TIPS - Use Shift-G to access the grid menu. Set the coarse grid to 0.1um, fine grid to 0.01um
Use Shift-Y to explain the design rules within a selected area
poly
nfet
ct
ndif
Figure 2a
Rules are:
i)
Poly minimum width = 0.24 µm
ii)
CT minimum width = 0.3 µm
iii)
CT_NDIF to NFET MIN, spacing = 0.22 µm
iv)
ALL_POLY_DIF MIN CT enclosure = 0.14 µm
Using these values
a.
L = 0.24 µm
b.
W = 0.3 µm + 2(0.14 µm) = 0.58 µm (0.60 µm acceptable)
Ldrain = 0.3 µm + 0.14 µm + 0.22 µm = 0.66 µm
AD = AS = Ldrain * W = 0.66 µm * 0.58 µm = 0.383 µm2 ≈ 0.4 µm2
d.
PD = PS = W + 2Ldrain = 0.58 µm + 2*0.66µm = 1.9 µm ≈ 2.0 µm
Note that the perimeter only includes W once and not twice!
c.
b) We desire a minimum sized CMOS inverter with a symmetrical VTC (V M=VDD/2) in the mmi25
technology. Calculate the following for the pull-up PMOS transistor in the design.
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Assume the following:
VDD = 2.5V, VM = 1.25V, and refer to Table 3.2 in the Draft Chapters
We will use equation 5.5 from the draft chapters:
kn'VDSAT , n(VM  Vt , n  12 VDSAT , n)
(W / L) p

(W / L)n kp'VDSAT , p(VDD  VM  Vt , p  12 VDSAT , p)
The gate lengths will be identical and thus we can calculate Wp = 2.02 µm,
AD = 1.33 µm2, and PD = 3.34 µm.
c)
Using the same minimum size inverter from part b), determine the input capacitance (i.e. the load it
presents when driven). Please calculate the capacitance during a transition. From these, determine the
total load capacitance that the inverter presents.
*Hint: Consider the Miller effect
You have three capacitances per transistor to consider on an inverter for input capacitance, gate to bulk,
gate to source and gate to drain. Cox = 6.0fF/µm2
PMOS:
Cgb
saturated = 2/3 (CoxLpWp) = 2.02 fF
triode = CoxLpWp = 3.03 fF
cutoff = CoxLpWp = 3.03 fF
Cgd
= COWP = (3.1 fF/µm)*(2.02 µm) = 0.606 fF
Cgs
= COWP = (3.1 fF/µm)*(2.02 µm) = 0.606 fF
NMOS:
Cgb
Cgd
Cgs
saturated = 2/3 (CoxLnWn) = 0.595 fF
triode = CoxLnWn = 0.885 fF
cutoff = CoxLnWn = 0.885 fF
= COWn = (3.1 fF/µm)*(0.58 µm) = 0.174 fF
= COWn = (3.1 fF/µm)*(0.58 µm) = 0.174 fF
If switching Cin = (Cgbp + Cgbn) + (Cgsp + Cgsn) + 2 (Cgdp + Cgdn) = 6.225 fF
The factor of 2 is due to miller effect
d) Using the g25 model provided in ‘~ee141/MODELS/g25.mod’, please verify the accuracy of your
results in part c by determining the total input capacitance in a high-low and a low-high transition with
HSPICE and comparing with your total capacitance in part c. Turn in your HSPICE input deck.
You'll notice there are four corners, TT, FF, SS, FS, and SF. These represent the different variation
extremes we can expect due to process variations. For example, TT stands for NMOS: typical, PMOS:
typical. FS stands for NMOS: fast, PMOS: slow etc. For this homework, please use the TT model.
To use these models, include the following in your HSPICE deck:
.lib '~ee141/MODELS/g25.mod' TT
Input SPICE Deck:
______________________________________________________________________________
HW #3, prob. 2d (Dietrich Ho, 9/4/2000)
*****begin DEFINITIONS*****
.lib '~ee141/MODELS/g25.mod' TT
.param vddp = 5
.param ln_min = 0.25u
.param lp_min = 0.25u
.param l_drain = 0.66
.param arean(w) = '(w*l_drain*1p)'
.param areap(w) = '(w*l_drain*1p)'
.param perin(w) = '((w*1u)+(l_drain*2u))'
.param perip(w) = '((w*1u)+(l_drain*2u))'
*****end DEFINITIONS*****
VDD vdd 0 vddp
IIN 0 in 1u
M1 out vin vdd vdd pmos L=lp_min W=2.023u
M2 out vin 0 0 nmos L=ln_min W=0.6u
.ic v(in) = 0
.meas t1 trig at=2 targ v(in) val=’vddp/2’ cross=1
.meas t2 trig v(in) val=’vddp/2’ cross=1 targ v(in) val=supply cross=1
.meas CinLH param=’1u*t1/(vddp/2)’
.meas CinHL param=’1u*t2/(vddp/2)’
.options post=2 nomod
.op
.tran 0.1ns 15ns
.END
_______________________________________________________________________________
Relevant Capacitances:
CinLH = 5.9780 fF
CinHL = 5.6659 fF
The discrepancy between the measured and calculated values is probably due to fluctuation in CGB. In
our hand calculations, it is often better to err on the pessimistic side. By choosing to use CGB =
CoxWL, this gives an upper bound.
CinLH is larger than CinHL due to the fact that the gate capacitance decreases when VGS is near VT. During the H-L
transition, the PMOS gate cap is at its minimum. Thus, since the PMOS transistor is considerably larger than the
NMOS, CinHL is smaller than CinLH.
e)
Determine VIH, VIL , NMH, and NML.
*Hint: The 2 parameters r and g vary proportionally with transistor width. The equations given are
derived with the minimum width in mind. (Please refer to eqn. 5.3 and 5.10 in the draft chapters for r
and g)
First find r using eqn. 5.3 of the reader and then g using eqn. 5.10. Remember to account for the size
difference by applying direct ratio.
r = 1.94
g = 30.2
VM = VDD/2 = 1.25V
Then use equations 5.7 to solve:
VIH = VM + (2.5-VM)/g = 1.29V
NMH = VDD – VIH = 1.21 V
VIL = VM – VM/g = 1.21V
NML = VIL = 1.21V
Problem #3
a)
Figure 3a depicts the Id – VOUT curve of a typical NMOS transistor
Figure 3b depicts the Id – VOUT curve of a typical PMOS transistor
Assume we use these FETs to create a CMOS inverter. Using this family of curves, graph the VTC,
and calculate VM, VIL, and VIH.
Top: Figure 3a, Bottom: Figure 3b
Problem 3a
If you’re interested, the input SPICE Deck used to create the family of curves and the VTC seen below
in Figure Solutions.2d can be found
Figure Solutions.2d
The simplest way to determine the input voltages is to note the points on the curve where the slope is –
1, which was defined in class. VM can be determined by noting the point of intersection between the
VTC and a linear curve with slope = 1.
VIL = 1.1V
NML = 1.1V
VIH = 1.4V
NML = 1.1V
VM = 1.25V
Input Spice Deck for Prob. 3, NMOS Id-Vout Characteristics:
_______________________________________________________________________
Hw #3, Prob. 3 - NMOS (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 0
vds vds 0 0
m1 vds vin 0 0 nmos w=1.0u l=0.25u
.dc vds 0 2.5 0.1 vin 0 2.5 0.5
.plot LX4(m1)
.option post=2 nomod
.END____________________________________________________________________
Input Spice Deck for Prob. 3, PMOS Id-Vout Characteristics:
_______________________________________________________________________
Hw #3, Prob. 3 - PMOS (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 0
vds vds 0 0
m1 vds vin vdd vds pmos w=3.0u l=0.25u
.dc vds 0 2.5 0.1 vin 0 2.5 0.5
.plot LX4(m1)
.option post=2 nomod
.END____________________________________________________________________
Input Spice Deck for Prob. 3, VTC:
_______________________________________________________________________
Hw #3, Prob. 3 - VTC (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 pulse 0 2.5 0 5n 5n 10n 10n
m1 vout vin vdd vdd pmos w=3.0u l=0.25u
m2 vout vin 0 0 nmos w=1.0u l=0.25u
.dc vin 0 2.5 0.1
.tran 1n 50n
.option post=2 nomod
.END___________________________________________________________________________
b) If we increase the W/L ratio of the pull-down NMOS (leaving the PMOS size fixed), in which direction
will the VTC shift?
The VTC will shift to the left.
c)
If instead, we increase the W/L ratio of the pull-up PMOS (and leave the NMOS the original size), in
which direction will the VTC shift?
The VTC will shift to the right.
d) Please explain how the resizing in b) and c) will affect the above I-V curves in each case and give an
intuitive explanation of how this affects the VTC of each.
If we increase the W/L of an NMOS or PMOS, it moves the I-V curves up (higher magnitude of current
for same input voltage). As such, a larger NMOS gives more pulldown “strength,” while a larger
PMOS gives more “pullup” strength.