King Saud University
EE - 417: VLSI Circuit Design
College of Engg.
Dept. of Electrical Engg.
Final Examination,
14.6.1429H (18.6.2008);
II Sem, 1428 – 29 H
Time: 3 hours
Note: Answer all questions. Do the work neatly.
Show your work clearly and explain every step (except for Question One).
The following may be used:
Layer
n-Diff
p-diff
Dep. Impl.
Poly
Contact
Metal
Code(Color)
Green
Yellow
Yellow
Red
Black
Blue
Code(Mono)
Question One: Choose the most correct answer and write its number in the answer book.
(20 pts.)
1. The first mask used in NMOS IC technology is:
(a) Metal
(b) Poly
(c) Dep. Implant
(d) Diffusion
2. In CMOS N-well process, which of the following transistors are fabricated directly in the substrate:
(a) PMOS
(b) NMOS
(c) CMOS
(d) None of them
3. In which of the following types of ASIC, only some (the top few) mask layers are customized:
(a) Gate Arrays
(b) CBIC
(c) Full Custom
(d) None of them
(c) Placement
(d) Routing
4. Which of the following steps produces a netlist:
(a) Design entry
(b) Logic Synthesis
5. In which of the following, a matrix of programmable interconnects surrounds the basic logic cells:
(a) CBIC
(b) FPGAs
(c) Full Custom
(d) None of them
6. The value of λ in 2 μm technology is:
(a) 4 μm
(b) 3 μm
(c) 2 μm
(d) 1 μm
7. In an 8 : 1 nMOS inverter, the pull up transistor ratio is 4 : 1 and the on-channel sheet resistance (NMOS) is
10 KΩ/Square. The on-channel resistance of the pull down transistor is:
(a) 10 KΩ
(b) 5 KΩ
(c) 20 KΩ
(d) None of them
8. A parity checker is used to indicate the number of a 1s (ones) in an input or word is -------- or -------:
(a) large, small
(b) long, short
(c) odd, even
(d) negative, positive
9. Multiplexers are complementary switches that may be used to --------- between a number of -------, thus
forming a multiplexer function:
(a) appear, outputs
(b) select, inputs
(c) isolate, gates
(d) buffer, stages
10. A shift register cell, a 1- transistor dynamic cell, a 3- transistor dynamic cell, and a pseudo- static register
cell are used to:
(a) create logic function
(b) store a single bit
(c) discharge a CL
(d) lower delay
(c) a static memory cell
(d) a current limiter
11. The JK flip- flop can be used as:
(a) a switch
(b) a driver
12. Which of the following pull-up transistors in an inverter gives least power dissipation:
(a) NMOS enhancement mode
(c) PMOS
(b) NMOS depletion mode
(d) PMOS as well as NMOS
13. If the gate of a pass transistor is driven by another pass transistor:
(a) there will be loss of logic level
(c) the delay will be too large
(b) the power loss will be high
(d) None of them
14.
In a butting contact between poly and diffusion, the output is available on:
(a) diffusion, poly and metal lines
(c) poly and metal lines only
(b) diffusion and poly lines only
(d) none of them
15. The details of four MOS VLSI designs are given below. Select the most regular design.
16.
17.
(a) No. of transistors = 5,000; No. of leaf cells = 4
(c) No. of transistors = 15,000; No. of leaf cells = 7
(b) No. of transistors = 7,000; No. of leaf cells = 6
(d) No. of transistors = 18,000; No. of leaf cells = 9
Choose the correct equation for an adder element:
(a)
Sk  H k .C k 1  H k .Ck 1
(c)
Sk  H k .C k 1  H k .C k 1
(b)
Sk  H k .Ck 1  H k .Ck 1
(d)
Sk  H k .C k 1  H k .Ck 1
To prevent charge sharing in dynamic CMOS logic, the inputs:
(a) Should not change during the "ON" period of the clock..
(b) Should not change during the "OFF" period of the clock.
18.
(c) Should change while being cascaded.
(d) Should not exceed 4 in number
Which of the following is correct?
(a) Whenever metal crosses a diffusion line, a transistor is formed.
(b) Metal can cross diffusion but not poly lines.
(c) Metal can cross poly but not diffusion lines.
(d) Metal can cross both poly and diffusion lines.
19.
The stick diagram shown on the left represents:
VDD
(a)
A
pseudo-static memory cell
D
S
(b)
A
three – transistor dynamic memory cell
(c)
Row Select
Red Write
A
one – transistor dynamic memory cell
(d)
Plate
N
one of the above
20.
The Figure shown on the left shows:
(a) An NMOS pseudo- static D flip- flop memory cell.
(b) A CMOS pseudo- static JK flip- flop memory cell.
(c) A CMOS pseudo- static D flip- flop memory cell.
(d) A Switch logic JK flip- flop memory cell
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Question Two:
(20 pts.)
1.
Sketch the cross sectional view of an NMOS IC Transistor.
2.
Sketch the colored stick diagram of a 2-input CMOS NOR gate.
3.
Sketch tentative floor plan for a 4-bit data path.
4.
Draw the circuit diagram of a pass transistor based 3- input nMOS AND gate.
5.
Select two main objectives of ASIC technology from the following and write them in your answer book:
(a) To reduce cost to acceptable limits at low volumes of production.
(b) To reduce turn around time to acceptable limits.
(c) To optimize the design and fabrication.
(d) To reduce power dissipation.
6.
Calculate the optimum delay for a 64 bit carry select adder. The propagation delay through the adder
element and the multiplexer both are equal to 2 ns.
7.
For the given 5 μm transistor, calculate the
peripheral capacitance of the drain, assuming
Cperiph = 8 X 10–4 pF/μm.
9λ
2λ
2λ
5λ
8.
The transfer characteristics of an inverter is
shown on the right.
Draw the circuit diagram of the inverter.
9.
Draw the color stick diagram for the
layout shown in the figure.
3
6λ
Drain
2λ
10.
The stick diagram for an nMOS pseudostatic memory cell, with provision of a
second bus is given in the figure.
Draw the circuit diagram of the cell.
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Question Three:
(10 pts.)
Consider two NMOS inverters with the following geometry:
Lpu1 = 8 Lpu2 = 16, Wpu1 = Wpu2 = 2, Lpd1 = Lpd2 = 2, 4Wpd1 = Wpd2 = 8.
The inverters are cascaded to drive a capacitive load CL = 24Cg.
(i)
What is the overall delay?
(ii) What are the ratios of each inverter?
(iii) If strays and wiring were accounted for, an increase of the capacitance to ground across the output of each
inverter by 6Cg would result. What will be the pair delay? Assume  = 0.3 nsec.
Question Four:
(10 pts.)
Scaling down of devices involves shrinking dimensions of transistors, interconnections and the separation
between features, and by adjusting the doping levels and supply voltages. Let 1/ be used to scale D and VDD
and 1/ be used to scale all other linear dimensions, both vertical and horizontal to the chip surface.
Find, with the aid of some calculations, the effect of scaling on the following key parameters of MOSFET
devices: the current density (J), gate capacitance (Cg), gate delay (Tg), static (Ps) and dynamic (Pd) power
dissipation and power-delay product (PT). Use the combined voltage and dimension scaling model.
Question Five:
(10 pts.)
Draw the transistor circuit diagram, construct a color-coded stick diagram, and identify a suitable standard
cell(s) to represent the design of the following NMOS structures indicating the pull-up/pull-down ratio in each
case:
(i) An 8:1 multiplexer circuit incorporating an enable control line.
(ii) A 4x4-bit barrel shifter.
What are the most attractive common features among these designs?
Question Six:
(10 pts.)
(a) Write the three main factors used to make a comparative assessment of various storage elements used in
VLSI.
(b) The mask layout of a shift register cell is given in
the figure on the right. Two such cells are needed
for one bit. Find:
(i) The area required per bit.
(ii) The number of bits stored on a 5 mm X 5 mm
chip.
(iii) The approximate power dissipation of the chip
if it works at 100 MHz.
(iv) Volatility.
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