Digital Logic/Design. — L. 11
11
May 8, 2006
Synchronous State Machines
• Synchronous (finite) state machines are also known as clocked sequential circuits.
• Registers and counters are examples of specialised synchronous sequential circuits.
• Recall that in a general case we have two types of state machines, Mealy and Moore, that differ in the
way the output signals are form.
X
state equations: Q(t + 1) = f (Q(t), X(t))
D FFs excitation eqs: D(t) = f (Q(t), X(t))
Excitation
(next state)
circuit
Output equations:
Mealy:
Moore:
Y (t) = g(Q(t), X(t))
Y (t) = g(Q(t))
X
Excitation
(next state)
Output
circuit
D[n−1:0]
clk
rst
• In the Moore state machine the output signals
are re-coded state signals.
• In the Mealy state machine the output signals
depends both on state signals and input signals.
Y
D[n−1:0]
D FFs
clk
rst
Q[n−1:0]
D FFs
Q[n−1:0]
Output
circuit
Y
• Typically, state machines are primarily described by state diagrams.
• State diagrams are converted into state and output tables from which the structure of the excitation
and output circuits can be derived.
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A.P. Papliński
Digital Logic/Design. — L. 11
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May 8, 2006
Example of a Moore state machine
x
• Consider a Moore state machine described by the
following symbolic state diagram:
x
a
ya
x
• The state machine has a single input, x, three states
labeled a, b, c and a single binary output y ∈ {ya, yb}
• Unlike in the asynchronous case, the states can be flexibly
coded, simplicity of the excitation circuit being the only
limitation.
• We start with state assignment replacing symbolic names
of the states with their binary equivalent.
This results in the following state state diagram:
• The state machine now has two D flip-flops q1, q0.
• Note that in the synchronous case the machine is in any
given state for at least one clock cycle.
A.P. Papliński
x
x
• At least two state signals, say q1, q0 are required to code
three states.
b
yb
x
c
yb
x
x
00
0
01
1
x
x
x
x
11
1
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Digital Logic/Design. — L. 11
May 8, 2006
• The next step is to convert the state diagram into the state
and output equations.
x
x
• the excitation table for D flip-flops is identical with the
state table.
x
0
1
0
1
0
1
0
1
Q1
0
0
0
0
1
1
1
1
Q0 D1
0 0
0 0
1 0
1 1
0 −
0 −
1 0
1 0
D0
0
1
0
1
−
−
1
0
Q1
0
0
1
1
Q0
0
1
0
1
00
0
01
1
x
x
x
y
0
1
−
1
x
11
1
Excitation and output equations:
• Resulting Karnaugh maps
D1
Q1Q0
x 00 01 11 10
0 0 0 0 −
1 0 1 0 −
D1 = x · Q1 · Q0
D0 = x · Q1 + x · Q1 = x ⊕ Q1
y = Q0
D0
Q1Q0
x 00 01 11 10
0 0 0 1 −
1 1 1 0 −
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A.P. Papliński
Digital Logic/Design. — L. 11
May 8, 2006
• Excitation and output equations:
Logic diagram:
D1 = x · Q1 · Q0
D0 = x · Q1 + x · Q1 = x ⊕ Q1
y = Q0
• The excitation circuit generates input signals to the
flip-flops
• These signals are clocked in during the rising edge of
the clock.
x
Excitation circuit
clk
D1
D
C
Q
• The output circuits is trivial in this example, but in
general the output signals are generate by a
combinational circuit from the state signals.
Q1
D0
D
C
Q
Q0
y
• Timing diagram:
clk
x
Q
A.P. Papliński
a
a
b
c
b
a
b
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Digital Logic/Design. — L. 11
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VHDL specification of the Moore state machine
library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY MSTM IS
PORT ( x, clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
y : OUT STD_LOGIC
) ;
END MSTM ;
ARCHITECTURE behv OF MSTM IS
---
TYPE states IS (sa, sb, sc) ;
SIGNAL D : states := sa ;
SIGNAL
-- a "hard"
CONSTANT
CONSTANT
CONSTANT
-- encoding
CONSTANT
CONSTANT
D, stt : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
encoding of states:
sa : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ;
sb : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ;
sc : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;
of output signals
ya
: STD_LOGIC := ’0’ ;
yb
: STD_LOGIC := ’1’ ;
BEGIN
-- to synthesize edge-triggered flip-flops
clkd: PROCESS ( clk )
BEGIN
IF clk’EVENT AND clk = ’1’ THEN
stt <= D ;
END IF ;
END PROCESS clkd ;
-- the stm process describes the transitions between states -- and the output signals
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Digital Logic/Design. — L. 11
May 8, 2006
stm: PROCESS ( Q )
BEGIN
-- default assignments
D <= Q ;
y <= ya ;
CASE stt IS
-- state transitions and output signals
WHEN sa =>
y <= ya ;
IF x = ’0’ THEN
D <= sa ; ELSE
END IF ;
D <= sb ;
WHEN sb =>
y <= yb ;
CASE x IS
WHEN ’0’
=>
WHEN OTHERS =>
END CASE ;
WHEN OTHERS =>
y <= yb ;
D <= sa ;
D <= sc ;
--- when sc
CASE x IS
WHEN ’0’
=>
WHEN OTHERS =>
END CASE ;
D <= sb ;
D <= sa ;
END CASE ;
END PROCESS stm ;
Q <= stt ;
END behv ;
A.P. Papliński
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Digital Logic/Design. — L. 11
x / ya
Example of a Mealy state machine
x / yb
– a single input, x,
x / yb
d
– binary output y ∈ {ya, yb, yc, yd} that will be coded
by two output signals y1, y0
x / 00
x / 01
11
x / 10
• Labeling of the output signals might be confusing: it is the
state that arrow originates from that generates the output
signal together with the input signal.
01
x / 10
00
x / 10
• Note that the output signals depend now on both the state
signals and the input signal(s).
• After the state and output assignment we have the
following state state diagram:
c
x / ya
x/
– four states labeled a, b, c, d that will be coded using
(at lest) two state signals q1, q0, and
x / yc
yd
x / yc
• The state machine has
b
x / yc
a
• Consider a Mealy state machine described by the
following symbolic state diagram:
x/
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May 8, 2006
x / 01
11
x / 00
10
A.P. Papliński
Digital Logic/Design. — L. 11
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May 8, 2006
• Timing diagram
• Note that output signals change in response to a change in both input signals and state signals.
• The next step is to convert the state diagram into the state and output equations.
• the excitation table for D flip-flops is identical with the state table.
A.P. Papliński
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Digital Logic/Design. — L. 11
May 8, 2006
x / 00
The excitation (state) and output tables:
Q1
0
0
0
0
1
1
1
1
x / 01
Q0
0
0
1
1
0
0
1
1
y1
0
0
1
1
1
0
0
1
y0
0
1
0
1
0
0
1
0
00
01
x / 10
x
0
1
0
1
0
1
0
1
x / 10
D0
0
1
0
1
1
1
1
0
11
Q0 D1
0 0
0 0
1 1
1 1
0 0
0 1
1 1
1 0
x/
Q1
0
0
0
0
1
1
1
1
x / 10
x
0
1
0
1
0
1
0
1
x / 01
11
x / 00
10
Resulting Karnaugh maps:
D1+
Q1Q0
x 00 01 11 10
0 0 1 1 0
1 0 1 0 1
D0+
Q1Q0
x 00 01 11 10
0 0 0 1 1
1 1 1 1 0
y1+
Q1Q0
x 00 01 11 10
0 0 1 0 1
1 0 1 1 0
y0+
Q1Q0
SR 00 01 11 10
0 0 0 0 1
1 1 1 0 0
Write out the logic equations as an exercise.
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A.P. Papliński
Digital Logic/Design. — L. 11
May 8, 2006
Logic diagram:
Excitation and output
x
logic circuit
(3 inputs 4 outputs)
D1
clk
C
D
Q
D0
C
y1
y0
Q0 Q1
D
Q
Q1
Q0
Write a VHDL description as an exercise
A.P. Papliński
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