New Generation
of
Virtual Substrates
T. Grasby
Dept. of Physics, University of Warwick
SiNANO Workshop, Montreux, Sept 2006
Straining Silicon with a Virtual Substrate
Device Layer
unstrained silicon
Si template (i.e. wafer)
strained silicon (biaxial tensile)
z
SiGex(z)
New template
(virtual substrate)
Si wafer
SiNANO Workshop, Montreux, Sept 2006
Why Global Strain?
Non, Non
• Uniaxial process-induced strain more
effective, more flexible
• Riddled with defects
• Expensive to produce
SiNANO Workshop, Montreux, Sept 2006
Why Global Strain?
GLOBAL STRAIN FOR EVER
Enables high (biaxial) stress levels ~ 0.9 GPa per 10% Ge
concentration (y)
•
• Comparably high uniaxial strain via patterning
• Hybrid strain regime – global + process induced top-up
• Platform for n-sSi/p-SiGe dual channel CMOS devices
• Contender for 32-22nm node FDSOI
• Needed for R&D on strained Ge devices
• Route to Si-Ge-GaAs integration?
SiNANO Workshop, Montreux, Sept 2006
Big Questions
 is the quality there?
 is there a route to production?
SiNANO Workshop, Montreux, Sept 2006
First Generation VS (linear Ge grade)
– Quality Issues
Ge conc(y) ~ 20% - good for nMOS
performance
→ threading (field) dislocation density
(TDD) ≥ 105 cm-2
→ pile-up densities (PUD) ~ 0.1 – 10
cm-1
→ surface roughness ~ 1 – 3 nm
 involve CMP
SiNANO Workshop, Montreux, Sept 2006
Linear Grading – State of the Art
1.00E+06
12
10
RMS
RMS roughness (nm)
TDD (cm-2)
Field TDD
8
1.00E+05
6
4
2
Pile-up TDD
1.00E+04
0
15
20
25
30
35
40
45
50
55
Germanium composition (%)
From Y. Bogumilowicz et al., LETI and IQE
SiNANO Workshop, Montreux, Sept 2006
Linear Grading – State of the Art
1.00E+06
12
10
RMS
TDD (cm-2)
8
1.00E+05
6
4
RMS roughness (nm)
Field TDD
2
Pile-up TDD
1.00E+04
0
15
20
25
30
35
40
45
50
55
Germanium composition (%)
From Y. Bogumilowicz et al., LETI and IQE
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading
Ge Concentration
20%
Linear grade
10%
0
2
4
6
8
Thickness (mm)
SiNANO Workshop, Montreux, Sept 2006
UK SiGe:C Epitaxy Centre
SS-MBE
MBE - V90S-ANT
LP-CVD - ASM Epsilon 2000E
...from Lab to Fab
GS-MBE/-CVD mode
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – development work (SS-MBE)
30% - 3 tier
SiNANO Workshop, Montreux, Sept 2006
Terrace Graded - TEM
60% 6 Tier
SiNANO Workshop, Montreux, Sept 2006
LG 30%
≈105 cm-2 TDD
Pile-up ≈1 cm-1
SiNANO Workshop, Montreux, Sept 2006
Defect reveal in 104 cm-2 range
TDD ≈ 4 x 104 cm-2
SiNANO Workshop, Montreux, Sept 2006
Defect Reveal in 103 cm-2 range
LG 15%, 850ºC
Pseudo Pile-up
EPD = 6x103
SiNANO Workshop, Montreux, Sept 2006
Hardly an etch pit in sight!
TD
TDD ≈ 3x103 cm-2
PUD = 0
SiNANO Workshop, Montreux, Sept 2006
LG 40%
TDD ≈ 106 cm-2
Pile-up ≈ 5cm-1
SiNANO Workshop, Montreux, Sept 2006
TG 40%
TDD ≈ 3x105 cm-2
Pile- up = 0?
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – Elimination of Pile-ups?
SiPHER Analysis
TG (3 tier) up to 30% (SS-MBE)
Photoluminescence image
Surface image
6x6 mm area
Pile-up density: ≤ 0.1 cm-1
Measurements taken by Accent Optical Technologies near wafer centres
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – Elimination of Pile-ups?
SiPHER Analysis
3 tier up to 30% (SS-MBE)
TG
Photoluminescence image
LG
Surface image
6x6 mm area
Pile-up density: ≤ 0.1 cm-1
Photoluminescence image
2x2 mm area
Pile-up density: 3.5 - 6 cm-1
Measurements taken by Accent Optical Technologies near wafer centres
SiNANO Workshop, Montreux, Sept 2006
How does Terrace Grading do it?
LG
LG
SiNANO Workshop, Montreux, Sept 2006
What can Terrace Grading do?
LG
LG
TG
TG
SiNANO Workshop, Montreux, Sept 2006
30% Terrace Graded Properties
(MBE growth)
High T growth (850  790C)
y = 0.3
TDD (cm-2)
LG
High T
TG
High T
3.5x105
2x105
PUD (cm-1)
~ 1.0
0
RMS roughness
(nms)
(20x20μm)
~5
3.2
SiNANO Workshop, Montreux, Sept 2006
30% Terrace Graded Properties
(MBE growth)
High T growth + anneal
y = 0.3
TDD (cm-2)
LG
High T
+ anneal
3.5x105
 3x105
TG
High T
+ anneal
2x105
 5x103
PUD (cm-1)
~ 1.0
0
RMS roughness
(nms)
(20x20μm)
~5
3.2
SiNANO Workshop, Montreux, Sept 2006
30% Terrace Graded Properties
(MBE growth)
Low T growth 800 700C
y = 0.3
TDD (cm-2)
LG
High T
(850-790°C)
3.5x105
 3x105
TG
High T
+ anneal
2x105
 5x103
TG
Low T
3x103
PUD (cm-1)
~ 1.0
0
0
RMS roughness
(nms)
(20x20μm)
~5
3.2
1.9
SiNANO Workshop, Montreux, Sept 2006
30% TG
TD
TDD ≈ 3x103 cm-2
PUD = 0
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – (SS-MBE)
TDD for y  50%
High T growth - 850790C
SiNANO Workshop, Montreux, Sept 2006
Transfer to CVD
• TG virtual substrates up to y = 0.2 grown on ASM
Epsilon 2000E™ RP-CVD reactor using SiH4,
SiCl2H2 and GeH4 precursors.
• Optimisation work - growth temperatures, growth
rates, strain gradients, no. of terraces, terrace widths,
throughput, etc
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading Properties (CVD) y→0.2
Sample 1065: Ge & Si fraction Job:AA1704
0.22
1.02
Ge (fraction)
Si (fraction)
1.00
0.18
0.98
0.16
0.96
0.14
0.94
0.12
0.92
0.10
0.90
0.08
0.88
0.06
0.86
0.04
0.84
0.02
0.82
0.00
0
1000
2000
3000
4000
5000
6000
7000
8000
Si (fraction)
Ge (fraction)
0.20
0.80
9000
Depth (nm)
4 tiers
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading Properties (CVD) y→0.2
AFM images showing 10x10μm area and 2x2μm area
TD
Reciprocal space maps (000 and
220) of 2 tier TG 20% sample taken
with XRD
Typical etch pit image of TG sample capped with
10nm of strained silicon. TDD ~ 105
SiNANO Workshop, Montreux, Sept 2006
Pile-Up Free
TG (2 tier) up to 17% (LPCVD)
Photoluminescence image
Surface image
6x6 mm area
Pile-up density: 0
Measurements taken by Accent Optical Technologies
SiNANO Workshop, Montreux, Sept 2006
Terrace Graded Props (CVD) y = 0.2
y = 0.2
AdvanceSis
TDD (cm-2)
≈ 1x104
PUD (cm-1)
< 0.1
Relaxation (%)
> 96
RMS roughness
(nms)
(20x20μm)
< 1.8
Other Expert
Assessment
SiNANO Workshop, Montreux, Sept 2006
Terrace Graded Props (CVD) y = 0.2
y = 0.2
AdvanceSis
Other Expert
Assessment
TDD (cm-2)
≈ 1x104
1.1x105
PUD (cm-1)
< 0.1
0.0
Relaxation (%)
> 96
--
RMS roughness
(nms)
(20x20μm)
< 1.8
1.65
SiNANO Workshop, Montreux, Sept 2006
Terrace Graded Props (CVD) y = 0.2
y = 0.2
AdvanceSis
Other Expert
Assessment
TDD (cm-2)
≈ 1x104
1.1x105
PUD (cm-1)
< 0.1
0.0
Relaxation (%)
> 96
--
RMS roughness
(nms)
(20x20μm)
< 1.8
1.65
SiNANO Workshop, Montreux, Sept 2006
Misfits at the sSi/VS interface
MD
TD
SiNANO Workshop, Montreux, Sept 2006
Misfits at the sSi/VS interface
MD
TD
…….but tsSi = 10nm which is < tc (17nm)
SiNANO Workshop, Montreux, Sept 2006
EPD Reveal in VS with sSi layer
Chemical etchant
TD
Strained silicon
MD
Etched surface
TD
Virtual substrate
Additional etch pit
 100% increase in EPD
SiNANO Workshop, Montreux, Sept 2006
Terrace Grading – basic studies (y→0.2)
(with sSi layer)…CVD
100
1.0E+06
Relaxation of upper terrace (%)
TDD (cm-2)
80
60
1.0E+05
y
0.2
0.1
40
20
0
1.0E+04
0
1
2
3
4
0.0
2
4
6
8
Thickness (μm)
5
Number of terraces
SiNANO Workshop, Montreux, Sept 2006
50% terrace graded (for sSi)
TDD = 3x105 cm-2
PUD = 0
SiNANO Workshop, Montreux, Sept 2006
80% terrace graded (for sGe)
TDD = 3x105 cm-2
PUD = 0
SiNANO Workshop, Montreux, Sept 2006
Terrace graded VSs – smoother!
CMP
LG data from LETI
….and no CMP
SiNANO Workshop, Montreux, Sept 2006
• Terrace grading
The Future
Heralds a new generation in VS quality:
eliminates pile-up
low TDD
potential to avoid CMP
route to production√
• Current work
Examining new designs which directly manage the relaxation process:
→ thinner virtual substrates
→ TDD and PUD → zero
→ smooth enough for wafer bonding
• And finally
Still a lot of parameter space to be explored
– and if you thought Si-Ge relaxation was fully understood ..….……
SiNANO Workshop, Montreux, Sept 2006
THINK AGAIN!
SiNANO Workshop, Montreux, Sept 2006
Linkage with SiNANO
• Many VS-based sSi layers supplied to WP1 and WP2
partners for device processing
• VSs characterised by partners
• VS-based sGe layers supplied to partner for device
processing
• VS-based sSiGe and sGe layers to be supplied to Jeulich for
OI bonding trials
• VS work enabled a presence on PULLNANO project
SiNANO Workshop, Montreux, Sept 2006
END
SiNANO Workshop, Montreux, Sept 2006