DCD4_Pipeline
Ivan Perić
University of Heidelberg
Germany
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DCDB4_Pipeline
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Features:
Pipeline ADC (designed sampling rate ~ 50ns)
New digital block (designed for up to 640MHz, low power serializers)
Analog common mode correction (can be switched)
Temperature stabile reference
High precision calibration DAC
The measurement results on single chips are good
2
DCDBPip
TIA
ADC
200 µm
5 mm
3
Pipelined vs. Cyclic ADC
Algorithm:
Copy here copy there
Compare with threshold add reference
Subtract two outputs (duplicate)
Pipeline ADC
Memory cell
ADC1
ADC2
1
1
1
MSB cell
1
LSB cells
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
Hi
1
1
1
Lo
- Cyclic ADC approach
- Algorithm performed cyclically (ping pong wise)
by two memory cell pairs
- Two ADCs per channel
- Pipeline ADC approach
- 200ns sampling rate/ADC
- Algorithm performed as in production line by 8 memory cell pairs
- ADC clocked with 100MHz
- One ADC per channel
- 100ns sampling rate when clocked with 50MHz
- Designed for 50 ns sampling rate
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DCDB4_Pipeline
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Measurement results on 4.1. module
3 Columns are measured
6 and 7 are ok
1 – LSB does not work (wire bond problem)
Column 2 – one of the significant bits does not work (wire bond problem)
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DCDB4_Pipeline at 320MHz – new settings
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Measurements done at 320MHz
Settings:
On the generators:
VDDA: 2.15V (364mA)
GNDA: 0V
VDDD: 2.0V (176mA)
GNDD: 0V
AMPLOW: 1.7V (247mA)
REFIN: 1.05V (50mA)
Measured on sense lines:
VDDA: 1.86V
GNDA: 0.14V
VDDD: 1.864V
GNDD: 0.077V
AMPLOW: 0.485V
REFIN: 1.0
Power consumption ~ 1.33mW
Bias currents for DCDRO: 0.28mA (LVDSin) and 5.45mA (LVDSout)
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Test all ADCs – fit (-100 to 125)
first ADC’s Noise
100
INL of first ADC
1
DNL of first ADC
DNL [ADU]
Noise [ADU]
ADU
150
INL [ADU]
ADC Characterization
80
60
40
20
1.4
0
0.6
2
1.8
1.6
0.8
50
1.2
0
0.4
-20
1
-40
0.8
-50
0.6
-60
0.2
-100
0.4
-80
0.2
-100
10
15
20
25
-6
0
0
30
Gain of All ADCs
 10
5
10
15
20
25
-6
0
Mean Noise of All ADCs
Noise [ADU]
100
90
80
 10
30
5
10
15
20
25
-6
1.4
6
70
8
10
12
14
16
18
20
22
-6
24
DNL of All ADCs
5
4.5
1.2
 10
0
30
Peak-to-Peak INL of All ADCs
INL [ADU]
5
DNL [ADU]
 10
0
Gain [nA/ADU]
10
9
4
8
3.5
7
3
6
2.5
5
2
4
1.5
3
1
2
1
60
0.8
50
40
0.6
30
0.4
20
0.2
0.5
20
40
60
80
0
0
100
Gain vs. ADC Position
16
40
60
80
100
Mean Noise vs. ADC Position
80
78
14
20
76
12
10
72
8
70
68
6
20
40
60
80
100
16
1.4
14
4.5
14
1.2
4
12
1
10
0.8
3
8
0.6
6
2.5
2
6
0.4
4
0
62
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
60
60
80
100
16
5
4.5
14
4
3.5
10
3
8
2.5
2
6
1.5
4
1.5
4
64
2
40
12
3.5
10
8
20
DNL vs. ADC Position
5
66
4
0
0
Peak-to-Peak INL vs. ADC Position
16
12
74
1
0
0
DCDB physical ADC location
0
0
DCDB physical ADC location
10
DCDB physical ADC location
…
DCDB physical ADC location
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1
0.2
2
0
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
0
2
0
0.5
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L13R14 14 15L15R
L R L R
L R
0
1
2
0
0.5
0L 0R 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R 7L 7R 8L 8R 9L 9R 10L10R11 11 12 12 13L 13R14 14 15L 15R
L R L R
L R
0
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Test all ADCs – fit (-100 to 125)
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ADC gain 72nA/LSB (~110e @ gq 650pA/e)
Noise: ~0.55LSB (60e @ gq 650pA/e)
90
80
1.4
1.2
70
DNL of All ADCs
5
DNL [ADU]
100
Peak-to-Peak INL of All ADCs
INL [ADU]
Mean Noise of All ADCs
Noise [ADU]
Gain [nA/ADU]
Gain of All ADCs
4.5
10
9
4
8
3.5
7
1
60
3
50
40
0.6
30
220e
6
275e
0.8
2.5
5
2
4
1.5
3
1
2
0.5
1
0.4
20
0.2
10
0
0
20
40
60
80
100
0
0
20
40
60
80
100
0
0
20
40
60
80
100
0
0
20
40
60
80
100
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Test one ADC – fit (-100 to 125)
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DCDB4_Pipeline at 320MHz
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VDDA varied +/- 50mV and AMPLOW +/- 50mA
No influence on the chip
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DCDB4_Pipeline
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3 out of four columns tested
Noise ~40nA@320MHz
A few channels sensitive – they show missing codes around values -64 or 64
The problem is old, it exists since DCD1, now it has been understood – poor matching of
transistors, the fix is to increase the setting VPSuorce with respect to VPFB and VPSource2 (good
values for Sc., FB, Sc2.: 80, 70, 70)
VDDA, AMPLOW do not influence the behavior significantly
REFIN should be correct within +/- 50mV
Analog CMC tested and works
Band-Gap reference works
Current consumption at 320MHz:
VDDA: 364mA+AMPLOW (DCDB3 286mA+AMPLOW) (change +78mA)
AMPLOW: 247mA (DCDB3 182 mA) (change +65mA)
VDDD: 176mA (DCDB3 268mA) (change -92mA)
Total change: +51mA
DCDB4 tested even at 500MHz clock rate (64ns sampling time) and works
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