Boolean Algebra
Mathematical system used to
manipulate logic equations.
Boolean Logic
Boolean Algebra
CS.352.F12
● Boolean: deals with binary values
(True/False, yes/no, on/off, 1/0)
● Algebra: set of operations to manipulate
values and evaluate expressions
Board: Construct Truth Tables
Boolean Functions
Truth Table Representation
Boolean Expression
A Boolean function is a function that operates
on binary inputs and returns binary outputs.
A Truth Table is the enumeration of all the
possible outputs of a Boolean function given
all possible input values.
A Boolean expression the application of
Boolean operators over set of variables.
● Play a central role in the specification,
construction, and optimization of
hardware architectures.
x
y
z
f(x, y, z)
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1. And: x * y is 1 exactly when both x and y
are 1
2. Or: x + y is 1 exactly when either x or y or
both are 1
3. Not: x' is 1 exactly when x is 0
Exercise 1: Boolean Expression -> Truth
Exercise 1: Boolean Expression -> Truth
Exercise 1: Boolean Expression -> Truth
Tables
Tables
Tables
Construct truth tables for the following boolean
expressions:
1. f(x, y) = x' + y
2. f(x, y, z) = (x * y) + (y * z')
1. f(x, y) = x' + y
2. f(x, y, z) = (x * y) + (y * z')
x
y
f(x, y)
x
y
z
f(x, y, z)
0
0
1
0
0
0
0
0
1
1
0
0
1
0
1
0
0
0
1
0
1
1
1
1
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
Exercise 2: Truth Table -> Canonical
Exercise 2: Truth Table -> Canonical
Canonical Representation
Representation
Representation
Every Boolean function can be expressed
using at least one Boolean expression called
the canonical representation:
Construct the canonical representation from the
following truth table:
f(x, y, z) = x'yz' + xy'z' + xyz'
For each row in truth table where output is 1, construct
a term by And-ing together the variables of that row,
and then Or all of these terms to form a Sum of
Products.
Every Boolean function, no matter how complex, can
be expressed using three Boolean operators only: And,
Or, and Not.
x
y
z
f(x, y, z)
x
y
z
f(x, y, z)
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
Minimization
While there is only one truth table
representation for every Boolean function, there
may exist multiple boolean expressions.
Minimization: Algebraic Laws
A * 1 = A
Identity
A + 0 = A
A + 1 = 1
Annulment
A * 0 = 0
A + A' = 1
Complement
For economic reasons, we usually want to
minimize or reduce the number of logical
operators used in our boolean expression.
Minimization: More Algebraic Laws
Associative Law
A * B * C = (A * B) * C = A * (B * C)
A * B * C = B * A * C = ...
A + B + C = B + A + C = ...
Distributive Law
A * (B + C) = (A * B) + (A * C)
A + (B * C) = (A + B) * (A + C)
DeMorgan's Law
(A * B)' = A' + B'
(A + B)' = A' * B'
A + A = A
A * A = A
Exercise 3: Minimize with Algebraic Laws
Exercise 3: Minimize with Algebraic Laws
Simplify the following Boolean function:
f(x, y, z)
factor
factor
complement
identity
distribute
complement
identity
A + B + C = (A + B) + C = A + (B + C)
Commutative Law
A * A' = 0
Indempotent
f(x, y, z) = x'yz' + xy'z' + xyz'
=
=
=
=
=
=
=
=
x'yz' + xy'z' + xyz'
z'(x'y + xy' + xy)
z'(x'y + x(y' + y))
z'(x'y + x(1))
z'(x'y + x)
z'((x' + x) * (y + x))
z'((1) * (y + x))
z'(y + x)
Board: Simplify Expression
Minimization: Karnaugh Maps
Board: Simplify Expression
Minimization: Karnaugh Maps (4 inputs)
Logic graph where all logic domains are
continuous, making logic relationships easy to
identify.
Logic Gate
Board: Draw Composite Gate
Logic Gate
Primitive Gates
Composite Gates
A gate is a physical device that implements a
Boolean function.
A primitive gate is a device that implements
an elementary logical operation.
We can chain together various primitive gates
to form larger and more complex composite
gates.
- Inputs and outputs of a Boolean Function =
Input and output pins of gate.
- Today, most gates are implemented as
transistors etched in silicon (chips).
And
Or
Not
These devices can be implemented by a variety of
technologies but their behavior is governed by the
abstract notions of Boolean algebra.
Multi-way Example:
And(a, b, c) = a * b *c = (a * b) * c
Exercise 4: boolean function -> gates
Exercise 4: boolean function -> gates
Interface vs Implementation
Implement the following boolean functions as
composite gates:
Draw composite gates on the board.
Each logic gate has a unique interface, but
may have multiple implementations.
1. Nand(a, b) = (a*b)'
2. Xor(a, b) = a*b' + a'*b
3. And(a, b, c, d) = a*b*c*d
Interface: the input and output pins exposed
to the outside world and the specified
behavior.
Implementation: the manner in which the
specified behavior is accomplished.
Board: draw composite gates
Board: Write Truth table & Boolean Expression
Board: Write Truth table
Interface vs Implementation:
Propagation Delay
Multiplexers
Demultiplexer
There is always a delay in a change in the
input of a gate to the corresponding change in
the output of the gate.
A multiplexer is a three-input gate that uses
one of the inputs, called the "selection bit", to
select and output one of the other two inputs,
called "data bits".
Opposite of a multiplexer; it takes a single input
and channels it to one of two possible outputs
according to a selector bit.
Decoder
Exercise 5: multiplexer
Exercise 5: multiplexer
A combinational circuit that converts binary
information from n input lines to a maximum of
2N unique output lines.
Implement a 4-to-1 multiplexor.
1. Use 2-to-4 decoder and 4 And gates and an
Or gate
Example:
Serial And vs Parallel And
2. Use 4 And3 gates and an Or gate
3. Use 3 2-to-1 multiplexers
Board: Sketch Multi-bit And
Multi-bit Gates
HDL
Computer hardware normally operates on
multi-bit arrays called buses.
Today's hardware designers use Hardware
Description Languages to plan and optimize
their chip architectures.
Building a multi-bit gate is easy: construct
arrays of n elementary gates.
HDL
- Simulate the hardware.
- Test the hardware.
- Model resource usage.
VHDL
Verilog
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
-- this is the entity
entity ANDGATE is
port (
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end entity ANDGATE;
-- this is the architecture
architecture RTL of ANDGATE is
begin
O <= I1 and I2;
end architecture RTL;
// And gate
module AND2(A, B, C);
input A;
input B;
output C;
assign C = A & B;
endmodule