Fast Algorithms for Retiming
1
Circuit Representation
[Leiserson, Rose and Saxe (1983)]
Circuit represented as retiming graph G(V,E,d,w)
– V  set of gates
– E  set of connections
– d(v) = delay of gate/vertex v, (d(v)0)
– w(e) = number of registers on edge e, (w(e)0)
2
Circuit Representation
Example: Correlator (from Leiserson and Saxe) (simplified)
+
0
7
Host
0
0

(x, y) = 1 if x=y
0 otherwise

0
2
3
3
0
Retiming Graph (Directed)
a
b
Circuit
Every cycle in Graph has at least one register i.e. no
combinational loops.
Operation delay

3
+
7
3
Preliminaries
e0
For a path p :
ek 1
e1
v0  v1 
vk 1  vk
k
d ( p)   d (vi )
(includes endpoints)
i 0
k 1
w( p)   w(ei )
i 0
Clock cycle
c  max {d ( p)}
p: w( p ) 0
0
7
Path with
0
0
w(p)=0
0
2
3
0
3
For correlator c = 13
4
Basic Operation
•
Movement of registers from input to output of a gate or vice versa
Retime by -1
Retime by 1
•
•
Does not affect gate functionality's
Mathematical formulation:
– r: V  Z, an integer vertex labeling
– wr(e) = w(e) + r(v) - r(u) for edge e = (u,v)
5
Basic Operation
Thus in the example, r(u) = -1, r(v) = -1 results in
0
0
0
0
u
3
v
0
3
7
1
0
0
2
•
•
7
1
1
v
u
3
0
3
For a path p: st, wr(p) = w(p) + r(t) - r(s)
Retiming:
– r: VZ, an integer vertex labeling
– wr(e) =w(e) + r(v) - r(u) for edge e= (u,v)
– A retiming r is legal if wr(e)  0, eE
6
Retiming for Minimum Clock Cycle
Problem Statement: (minimum cycle time)
Given G (V, E, d, w), find a legal retiming r so that
c  max {d ( p)}
is minimized
p: wr ( p ) 0
Retiming: 2 important matrices
• Register weight matrix
p
W (u, v)  min{w( p) : u 
 v}
p
• Delay matrix
p
D(u, v)  max{d ( p) : u 
 v, w( p)  w(u, v)}
p
7
Retiming for minimum clock cycle
0
7
0
v0 0
0
2
3
V1
V0
V1
V2
V3
W = register path weight matrix
(minimum # latches
on all paths between
u and v)
D = path delay matrix
(maximum delay on
all paths between
u and v)
0
3
V2
W
D
V0 V1 V2 V3
V0 V1 V2 V3
0222
0000
0200
0220
0 3 6
13 3 6
10 13 3
7 10 13
13
13
10
7
V0
V1
V2
V3
c    p, if d(p)   then w(p)  1
8
Conditions for Retiming
Assume that we are asked to check if a retiming exists for a clock cycle 
Legal retiming: wr(e)  0 for all e. Hence
wr(e) = w(e) = r(v) - r(u)  0 or
r (u) - r (v)  w (e)
For all paths p: u  v such that d(p)  , we require wr(p)  1
– Thus
k 1
1  wr ( p)   wr (ei )
i 0
k 1
  [ w(ei )  r (vi 1 )  r (vi )]
i 0
 w( p)  r (vk )  r (v0 )
 w( p)  r (v)  r (u )
Take the least w(p) (tightest constraint) r(u)-r(v)  W(u,v)-1
Note: this is independent of the path from u to v, so we just need to apply
it to u, v such that D(u,v)  
9
Solving the constraints
•
•
All constraints in difference-of-2-variable form
Related to shortest path problem
Correlator:  = 7
Legal: r(u)-r(v)w(e)
r (v0 )  r (v1 )  2
r (v1 )  r (v2 )  0
r (v1 )  r (v3 )  0
r (v2 )  r (v3 )  0
r (v3 )  r (v0 )  0
D>7:
r(u)-r(v)W(u,v)-1
r (v0 )  r (v3 )  1
r (v1 )  r (v0 )  1
r (v1 )  r (v3 )  1
r (v2 )  r (v0 )  1
r (v2 )  r (v1 )  1
r (v2 )  r (v3 )  1
r (v3 )  r (v1 )  1
r (v3 )  r (v2 )  1
V0
V1
V2
V3
W
D
V0 V1 V2 V3
V0 V1 V2 V3
0222
0000
0200
0220
0
0 3 6
13 3 6
10 13 3
7 10 13
13
13
10
7
7
0
v0 0
0
2
3
v1
0
3
V2
10
V0
V1
V2
V3
Solving the constraints
•
•
Do shortest path on constraint graph: (O(|V||E| )) (Bellman Ford Algorithm)
A solution exists if and only if there exists no negative weighted cycle.
Legal: r(u)-r(v)w(e)
r (v0 )  r (v1 )  2
r (v1 )  r (v2 )  0
r (v1 )  r (v3 )  0
r (v2 )  r (v3 )  0
r (v3 )  r (v0 )  0
Constraint graph
D>7:
r(u)-r(v)W(u,v)-1
r (v0 )  r (v3 )  1
r (v1 )  r (v0 )  1
r (v1 )  r (v3 )  1
r (v2 )  r (v0 )  1
r (v2 )  r (v1 )  1
r (v2 )  r (v3 )  1
r (v3 )  r (v1 )  1
r (v3 )  r (v2 )  1
-1
0
0
0
0
A solution is r(v0) = r(v3) = 0, r(v1) = r(v2) = -1
0
-1
2
r(0)
0
r(1)
1
1
-1
1
1
0,-1
0
r(2)
0,-1
-1
r(3)
0
1
11
Retiming
To find the minimum cycle time, do a binary search among the entries of
the D matrix (0(V E  logV))
0
7
0
v0 0
0
2
3
0
v1
V0
V1
V2
V3
3
V2
W
D
V0 V1 V2 V3
V0 V1 V2 V3
0222
0000
0200
0220
0
13
10
7
3
3
13
10
6 13
6 13
3 10
13 7
Retimed correlator:
+
+
Retime
Host
Host



Clock cycle
= 3+3+7=13

Clock cycle = 7
a
b
a
b
12
V0
V1
V2
V3
Retiming: 2 more algorithms
1. Relaxation based:
–
Repeatedly find critical path;
–
retime vertex at end of path by +1 (O(VElogV))
v
+1
Critical path
u
2. Also, Mixed Integer Linear Program formulation
13
Retiming for Minimum Area
Goal: minimize number of registers used
min N r   wr (e)
eE

 ( w(e)  r (v)  r (u ))
e:u  v
  w(e) 
eE
 (r (v)  r (u ))
e:u v
 N   (r (v)  r (u ))
u v
 N    r (v)(# fanin(v )  # fanout (v ) 
vV
 N   aV r (v )
vV
where av is a constant.
14
Minimum Registers - Formulation
Minimize:
 a r (v )
vV
v
Subject to: wr(e) =w(e) + r(v) - r(u)  0
•
Reducible to a flow problem
15
Problems with Retiming
• Computation of equivalent initial states
– do not exist necessarily
1
0
?
?
– General solution requires replication of logic for initialization
• Timing models
– too far away from actual implementation
16